SU781802A1 - Shaper-distributor of synchronizing signals - Google Patents

Description

The invention relates to computing and is intended to organize a synchronization system in a computer operation. Known multivibrator with quartz frequency stabilization, which can be used as a driver clock signals. J. This device has limited capabilities, since with its help it is impossible to organize a quantized, more than two stable phases. In addition, capacitors are used in this multivibrator. The charge time on the capacitors to a certain threshold voltage varies with the supply voltage, which impairs the stability of the sync signal. A known generator with delayed feedback, made on the frequency cable. In this generator, the input of a logic element is NOT connected via series-connected delay elements to its output. The delay elements are applied sections of the radio frequency cable. The pulse duration at the output of such a generator is equal to half the period T of generation, i.e. equal to the total delay of all elements of the delay. This generator has the ability to perform the function of the distributor without making any changes. A distinctive feature of this generator is the connection of the input and output of any of the three main components (one directly and the other through an inverter) to the inputs of an additional element 2I, the output of which provides the formation of a sync signal that differs in phase and duration from the pulses at the output of the generator. By increasing the number of such drivers over the additional elements 2I, it is possible to provide a symmetric distribution of pulses in phases 2. In connection with the appearance of logic elements operating at higher frequencies, the requirement for the stability of the dynamic parameters of the sync signals is increased. The closest to the present invention is a synchronizing signal distributor, comprising a generator of this frequency with an unregulated pulse length equal to the pause duration, performed on two series-connected delay elements connected between the input and the output of the logical element HE, the driver of the desired duration, performed on element 2I- NOT, the first input of which is connected to the output of the NOT generator element, and the second to the point between the first and second generator delay elements a time shifter between pulses at the outputs of the distributor, performed on ederzhi elements, the number of which is one element is less than the number of outputs of the distributor. In a known distributor, the number of outputs for the shifter between these outputs is one. The input of the third delay element is connected to the output of the 2I-NOT element of the pulse width generator, and the input and output of the same delay element are connected to you Odam of the distributor's former, high-frequency cable segments are used as elements of the delay, which together should provide a delay in time, equal to + (N-1), where T is the period of generation of synchronization signals of any of the outputs, and N is the number of outputs of the generator -distributor. The device possesses a relatively high stability of the dynamic parameters of the clock signals, achieved by reducing the number of logic elements, working sequentially in the chain of formation of the clock signals, up to two H. A disadvantage of this device is the complexity due to the application. a high-frequency cable of long length and relatively low stability of the dynamic parameters of the sync pulses due to the presence of two logic elements operating sequentially in the process of forming the clock signals. The purpose of the invention is to increase the stability of the dynamic parameters of bHyro-signals and simplify the circuit. In order to achieve this goal, the synchronization signal distributor-shaper containing the element. NAND, the output of which is connected to a chain of series-connected delay elements, whose inputs, besides the second, are connected to the outputs of the distributor, contains an RS trigger, the first input of the NAND element is connected to the output of the star delay element and the R input of the RS trigger, the input of the NAND element is connected to the output of the last delay element and to the 5-in 6 RS-flip-flop, the third input of the NAND element is connected to the unit / f output of the short-circuit TTG. - In FIG. 1 shows a functional electrical circuit formari- tion, a clock-distributor clock signal with four outputs; in fig. 2 shows time diagrams of the operation of the distributor with four, three and two outputs. Shaper-distributor contains series-connected elements, 1-5 delays. The number of delay elements is one more, than the number of outputs of the driver-distributor. On elements AND-NOT 6 and 7 is organized RS trigger. The input of the delay element 1 is connected to the output of the NAND element 8. The first input of the NAND element 8 is connected to the output of the delay element 1, to the input of the delay element 2 and to the input R of the RS flip-flop, i.e. with one of the inputs of the element AND-NOT b. The second input element AND-HE 8 is connected to the output of the last delay element, in this case with the output of the delay element 5 and to the input S of the RS flip-flop, i.e. with one of the inputs of the element AND-NOT 7. The third input of the element AND-HE 8 is connected to the single output of the RS flip-flop (output of the EAP 7 element). The inputs of the delay elements 1,3, 4, 5 are connected to the outputs of the driver-distributor. When establishing the norms for the delay elements and describing the operation of the device, it is assumed that the switching delay of the elements is equal to 0. In the next E-8, it is taken into account after describing the principle of operation of the device. To arrange a symmetrical phase shift between the device outputs, the delay of delay element 1 is equal to the set clock signal duration (t), the delay of delay element 2 is equal to and equal to the delay of the last delay element, in this case delay element 5. The delays of the remaining delay elements 3 and 4 are equal to each other and equal to each sum of the delays of delay elements 1 and 2, as well as the period T divided by the number of outputs N. The distributor operates as follows. From the function of the element, NAND 8 it is assumed that at its output there can be 1 (high potential level) when at least one of its inputs has a logical O (low potential level). At the output of the element, NAND 8 may be O only when all its inputs have 1. Under these conditions, the circuit in FIG. 1 provides switching element AND-NOT 8 at regular intervals. For example, when there is 1 at all inputs of the NAND element 8, and O at its output, then this condition may last for a time equal to the delay of delay element 1, since the appearance of the signal O at its

the output connected to the first input of the element IS-HE 8, flips the last one and sets it at its output 1. The occurrence O at the output of the delay element 1 through the input R of the RS flip-flop sets O at the output of the trigger connected to the third input of the element IS-NOT 8, confirming this with state 1 at the output of the INE element, it prohibits its switching. The information (logical level changes) from the output of the NAND element 8 is transferred through the serially connected delay elements 1-5. The occurrence of O at the output of the delay element 5 (last) through the second input of the element IS-HE 8 confirms state 1 at its output and simultaneously sets input 1 at the output of the trigger (element I-HE.7) at the output of the trigger. RS-flip-flop on the switching element AND. At the output of the delay element 5, a low logic level is DIVIDED. For a time equal to the delay of the delay element 1. After that, the output of the delay element 5 appears 1. At this time, at the outputs of all the support and trigger elements, a high logic level, which through the inputs of the IS-NE 8 element sets at its output O and the process repeats. Thus the IS-HE element 8 switches once after a time equal to the delay of delay element 1, and another time equal to the sum of the delays of all delay elements 1-5.

The multiphase clock signals are organized by connecting to the outputs of the driver-distributor of the inputs of all delay elements, except the second.,

Of the four output clock distributor, it is possible to obtain distributors that differ in the number of outputs. For example, to set up a distributor with 3 phase outputs (.fig. 1), output 4 is excluded and the input of delay element 4 is closed with its output (exclude delay element 4). To arrange a distributor with a two-phase output (Fig. 1 excludes output 3 and output 4 and closes the input of delay element 3 with output of delay element 4 (excluding delay elements 3 and 4), etc.

From the driver-distributor and the two-phase output, it is possible to obtain the driver-distributors with three-four and five-phase outputs. In this case, it is necessary that the delay of the second delay element be equal, the delay of the last delay element, and the delays of the intermediate delay elements are equal to each other and equal to each sum of the delay elements 1 and 2 delays.

781802

As delay elements in

This device can use the BacoKb-iracToTHOTS cable, so the output of the last delay element (delay element 5 in Fig. 1) is connected to the ground bus via a matching resistor. The NAND element 8 includes a transmitter (emitter follower) which, without violating the function of this element, provides current through a matched cable line.

RS-trigger in the process of switching-element AND-NOT 8 does not take part, so it does not affect the electrical parameters of the clock signals. This trigger protects the IS-NE element 8 from false switching when the pulse duration t $ - the delay in transmitting the signal of the IS-NE element 8 () is taken into account by reducing the delay of delay element 1 and delay element 5 (last) and increasing the delay of delay element 2 each by an amount equal to. The taps associated with the inputs and outputs of the NAND element 8 and the RS flip-flop obey the laws of the short line and do not need to be matched.

This distributor advantageously differs from the high-frequency cable known for its consumption, i.e. in size and complexity. The length of the high-frequency cable in this distributor provides a time delay equal to, instead of - - (N-I), available in the known device. This difference is more apparent with an increase in the number N of the outputs of the distributor driver.

The well-known distributor is also inferior in terms of the stability of the dynamic parameters of the clock signals, since two logical elements operate in sequence along the path of their formation, instead of the one in the device.

Claims (3)

1. Questions of radio electronics. Ser EVT, 1977, no. 12, s, 38. 2. Patent of the GDR No. 56256, cl. 21 a 36/00, 1967. 3. OST 4 WMO 305.000, ed. 1-71 damn. 24 (prototype).