SU780175A1 - Pulse frequency multiplier - Google Patents

Description

The invention relates to the field of automation and computer technology and can be used in information-measuring and control systems to reduce dynamic error when multiplying the pulse repetition rate.

A device for multiplying the pulse repetition rate, based on inversely proportional conversion to frequency, is a code proportional to the period of the input frequency, reduced by the number of times equal to the multiplication factor, and containing, for example, a reference frequency generator, 15 control unit, controlled frequency dividers, control counter and code transfer schemes [1].

The disadvantage of this device is the delay of one period 20 in the transmission of changing information, limited dynamic accuracy and scope mainly for slowly changing signals.

The closest technical solution to this invention is a device for multiplying the pulse repetition rate, comprising a control unit, a reference frequency generator, a control counter, four controlled 30

frequency dividers, each of which consists of a divider counter and a memory register connected by bits through a code transfer circuit, a frequency subtraction unit, a frequency summing unit, a binary frequency multiplier, a trigger with an input counter, three code transfer circuits and a switching element [2]. l

This device implements the following algorithm:

: (1) where Fjg. (T *) is the current value of the output of the ^1st multiplied frequency in the 4 + 1st period of the input signal, f (t /) is the instantaneous value of the input frequency in the middle of the i-ro period, if * (t.) * Is the increment instantly ^Ί value of the input frequency during the 1st period,) is the average value of the first derivative with respect to time? · the input frequency in the 1st period,

- multiplication coefficient, .780175 current time in the interval and <t <t4 ₊₁ beginning and end of ϊ + 1γο period

A signal proportional to the first time derivative of the input signal is obtained by dividing the signal increment proportional to the input frequency by a time interval equal to the ending period of the "input frequency at which the increment is received." The increment is obtained by subtracting two frequencies formed by inversely proportional conversion of two adjacent periods of the input frequency with a proportionality coefficient equal to K - the multiplication factor of the device.

Thanks to the introduction of corrective signals in half the increment of the instantaneous value of the input frequency during the period that has ended and the current increment of the input frequency proportional to the first time derivative of the input signal, the dynamic conversion error associated with the change in the input signal is reduced in the known device.

The signal obtained in this case is only approximately proportional to the first time derivative of the input signal, since the interval m- over which the increment is obtained can. be large enough, especially in the low-frequency range, and on it the first derivative can change its value. Therefore, expression (2) is a value proportional to the average value of the first time derivative in the ίth period of the input signal, which is necessary. time to attribute to the middle of the time interval T ;. By the end of the i-ro period, in case of a change in the first derivative, a methodological error is formed, equal to half the increment of the first derivative during the 1st period. In addition, in the prototype at the next time interval equal to. i + 1-st period. The signal received at the end of the Ι-th period, proportional to the first derivative, remains unchanged, while the derivative actually changes. Thus, the known device allows to obtain good metrological characteristics only for input signals that vary linearly or monotonically in time, which limits the scope of its application. For rapidly changing dynamic processes, the magnitude of the first derivative will vary between two converters (inside the period of the input frequency), therefore, the output signal in the known device will have a dynamic error depending on the magnitude of the second derivative of the input signal.

The aim of the invention is to reduce the dynamic error of the output signal.

This goal is achieved in that the pulse frequency multiplier containing the reference frequency generator, the output of which is connected to the input of the binary frequency multiplier and the first inputs of the three frequency dividers, the output of the first of which is connected to the first input of the pulse counter, the output of which through the first code transfer unit is connected to second in. the house of the second frequency divider, and the second pulse counter input is connected to the second input of the binary frequency multiplier and the first output of the control unit, the second, third and fourth outputs of which are connected respectively to the second input of the first code transfer unit, the third input of the second frequency divider and the second the input of the third frequency divider, the third input of which is connected to the output of the second code transfer unit, one input of which is connected to the first output of the second frequency divider, and the second input to the fifth output of the control unit, moreover, the output of the binary frequency multiplier is connected to the first input of the adder, the second input of which is connected to the first output of the subtractor, one input of which is connected to the second output of the second frequency divider, the second input is connected to the first output of the third frequency divider, and the second output is connected via a trigger to the third input adder and directly to the first input even. the fourth frequency divider, the second input of which is connected to the third output of the control unit, while the control inputs of the first and third frequency dividers are connected to the bus for setting the multiplication factor, three frequency dividers, a binary frequency multiplier, a code transfer unit, two subtractors, additional trig-. Ger and the adder, the first input of which is connected to the first output of the first subtractor, the second input is connected to the output of the fourth frequency divider and the first input of the second subtractor, the second input of which is connected to the output of the fifth frequency divider, and the output of the second subtractor is connected to the first input of the sixth frequency divider and through an additional trigger - with the third input of the additional adder, the fourth input of which is connected to the output of the second binary frequency multiplier, the first input of which is connected to the output of the reference clock generator a swarm input of which is connected by the output of the second transfer unit and the third input is connected to the fourth control block, with the frequency output, the second input connected to the first · output of the control unit, the third input connected to the output of the sixth frequency divider, one input of which is connected to the third input of the fourth frequency divider and the output of the first code transfer unit, the first input of the seventh frequency divider connected to the output of the reference frequency generator, the second input through the third code transfer unit connected to the second output of the third frequency divider, and the output of the seventh frequency divider through 'the third subtractor, the second input of which is connected to the first output of the third frequency divider, is connected to the first input of the fifth frequency divider, not connected with the code, the course of the additional adder is connected to the third input of the first binary frequency multiplier, and the fourth input of the adder is connected with the second output of the second frequency divider, the third inputs of the sixth and seventh frequency dividers are connected respectively to the third and sixth outputs of the control unit, the seventh output of which is connected to the second input ohm of the third code transfer block, and the input is connected to the input bus.

Each of the frequency dividers consists of sequentially connected memory register, code transfer element and pulse counter, the output of which is connected to the second input of the code transfer element.

In FIG. 1 is a block diagram of a pulse frequency multiplier ‘in FIG. 2 is a block diagram of a control unit.

The pulse frequency multiplier comprises a reference frequency generator 1, a pulse counter 2, frequency dividers 3-9, each of which is made of a pulse counter 10 and a memory register AND connected by bits through a code transfer element 12, binary frequency multipliers 13 and 14, subtractors 15- 17, adders 18 and 19, triggers 20 and 21, blocks 22-24 code transfer and block 25 of the control.

The pulse frequency multiplier operates as follows.

In the control unit 25, from each pulse of the sequence of the input frequency signal f _x (t), control signals are generated at the outputs 26-32 that determine the sequence of the frequency multiplier operating at the corresponding inputs of 26-32 'corresponding elements · From the output of the generator 1 pulses of high reference frequency f ₀ are fed to the counting inputs of the pulse counters of frequency dividers 3, 4, .5, 7 and binary frequency multipliers 13 and 14. In the divider 3, the reference frequency is divided by a constant coefficient K, which is the multiplication factor of frequency divider, and recorded in the form of a parallel code in the memory register 11 of the divider 3. In dividers 4, 5 and 7, the reference frequency is divided into variable coefficients written in the form of a parallel code in the memory registers after the end of each period of the input frequency. They have *. Pulses, following with a frequency: '₽ ₀ = ip from the output of divider 3, arrive at. counting input of the pulse counter 2, where they are summed up in a period of time equal to the current period-T. input signal, and formed by applying to the input 26 ^x zeroing of the pulse counter 2 control signals from block 25 after the arrival of each pulse of the input frequency '.' At the outputs of the discharges of the pulse counter 2 at the time of the survey, a coy is formed proportional to the end of the input signal period.

= ίδ-Τ.

. t · to 4 'counters transferred

This code, before zeroing 2 pulses through block 22 s of the code, is written to the memory register 11 frequency dividers 4,6,8 and 9, previously freed from previous information on the signal at inputs 28 * from block 25, by the signal at input 27 ^f from block 25 . Before resetting the memory register 11 of the frequency divider 4, the code в ^ _4 in it proportional to the previous i-1st period 1 / - is rewritten through the code transfer unit 23 by the signal at the input ZO'v previously freed by the signal at the inputs 29'memory registers dividers 5 and 8 of frequency. Accordingly, before zeroing the memory register of the frequency divider 5, its code Mt ^ _proportional to the ith 2nd period T? _G, is rewritten by the signal at the input 32 'through the code transfer unit 24, which is previously freed up by the signal at the input 31 ^x of the memory register of the frequency divider 7. Thus, after the end of the ΐ-th period of the input signal, the code Ш ^ will be written in the memory registers of the dividers 6 and 9, the code вτ; _γ will be written in the memory registers of the frequency dividers 5 and 8, _γ and the code will be written in the memory register of the frequency divider 7 H ^. ^ At the outputs of the frequency dividers 4, 5 and 7, frequencies will be formed respectively.

those. an increase in K times of the frequency corresponding to instantaneous values

input frequency in the middle of the periods T ^ '> and T ^ .d. Pulses with frequencies

F x (t) and F _x (t4_ ^) from the outputs of the dividers

4.5 frequencies are fed to the inputs of the subtractor 15, at the information output of which a sequence of pulses with an average frequency is formed

proportional to the increment of the input 10 signal during the ί-th period.

At the output of the subtractor 15, an increment sign signal is generated

F * () corresponding to the sign of the first derivative of the input signal 15 in the i-th period. Accordingly, pulses with frequencies F ^ it ^) and F _x (from the outputs of the frequency dividers 5 and 7 are fed to the inputs of the subtractor 16, the output of which forms a pulse sequence of 2Q with an average frequency f

proportional to the increment of the input signal during the i-1st period. In frequency divider 6, the frequency ΔF _x (t ^) supplied to its input from the output of subtractor 15 is divided by a factor of 30 I _Tch recorded in the memory register of divider 6 after the end of the ί-th period. At the output of the frequency divider 6, a pulse train with a frequency of 35 is formed

To ^1-k 'Yosh ι r ·' £ ₀ t · "£ ₀ ^g x 'i' proportional to the mean value of the first time derivative signal vhodno- ⁴ⁱ th to I-th period. In the frequency divider 8, the frequency arriving at its input from the output of the subtractor 16 is divided by the coefficient Νγ, beyond; written in the memory register of the divider, 45

8. At the output of the frequency divider 8, a pulse train with a frequency

K *) 50 _kt ~ ^Τ ί-ΐ I proportional to the average value of the first time derivative of the input signal in the -i-1st period. Pulses ⁵⁵ with frequencies. F * (c) and F _x from the outputs of the frequency dividers 6 and 8, the ith inputs of the subtractor 17 arrive, the output of which forms a pulse train with an average frequency of 60 proportional to the increment of the average value of the first derivative of the input signal during the ί-th period. From the output 65 of the subtractor 17, the frequency pulses AFj (t;) are fed to the inputs of the frequency divider 9 and trigger 20. The trigger 20 with the counting input performs the functions of a frequency divider by two, and a pulse sequence q of frequency ja F * () is formed at its output = = 5τγ · δ £ / (Κ) received at the input of the adder 18.

To obtain a signal proportional to the second time derivative of the input signal, i.e. the rate of change of the first derivative with respect to time, a signal proportional to the increment of the Average value of the first derivative is necessary, divided by the time interval over which this increment is obtained, i.e. for the ended period. The resulting signal will be proportional to the average value of the second time derivative of the input signal over the time interval of the ended period. Provided that the second derivative with respect to time is constant or monotonic, when derivatives of higher orders are equal to or close to zero, the received signal remains constant over the time interval the next period of the input frequency and will correspond to the instantaneous value of the second time derivative of the input signal in this interval. The indicated nature of the change in the input signal, when the value of the values of the first and second derivatives with respect to time is sufficient for its description, satisfies a wide class of dynamic systems in the field of measurement and regulation.

In the frequency divider 9 frequency

F _x (C) is divided by the coefficient recorded in the divider memory register.

• At the output of the frequency divider 9, a train of pulses is formed with a frequency = = X · _a = 7-4 (4) proportional to the average * о

I value of the second time derivative of the input signal in the i-th period. Pulses with a frequency of F. _x (t ·) are fed to the counting input of the control counter of the binary frequency multiplier 13, * the first input of which receives the frequency f ₀ from the generator output. The capacity of the counters of binary multipliers 13 and 14 of the frequency and is set equal to K - the multiplication factor of the device. In the controlled counter (binary frequency multiplier 13, the frequency F »(t ·) is integrated over the time interval ί + 1 period. The current code in this counter will be equal to where t varies from t _f HO t ₄ .

At the output of the binary multiplier 13 · frequency, a sequence of pulses is formed with an average frequency proportional to the current increment of the first derivative, depending on its rate of change, i.e. from the second derivative of the input signal with respect to time. The inputs of the adder 18 receives three sequences of pulses

() from the output of the frequency divider b, | ^ Fx (t ^) from the output of the trigger 20, and (t) from the output of the binary frequency multiplier 13. These frequencies, depending on the signal of the sign of the increment of the input frequency s <gn Д Fx (t _ή -), coming from the output of the subtractor 15, are algebraically summed, and at the output of the adder 18 a sequence of pulses is formed with the current frequency at ί + 1-st period proportional to the current value of the first time derivative. signal corrected by signals that compensate for the methodological and dynamic errors. Pulses 35 with a frequency F * (T _{1> +} ) from the output of the adder 18 are fed to the counting input of the control counter of the binary multiply. 14, the first input of which receives the reference frequency from the output of generator 40. At the output of the binary multiplier 14, a train of pulses is formed with an average frequency proportional to the current value of the increment of the input signal in time, compensated by the values of the methodological and dynamic errors. The inputs of the adder 19 receive three sequences of pulses F _x (t ^) from the output of the frequency divider 4, lF _x (t) - the output of the binary frequency multiplier 14 and - ^; --- from the trigger output 21. These frequencies, depending on the signal of the sign of the increment of the input frequency δ F _x - (t, ·), coming from the output of the subtractor 15, are algebraically summed, and at the output of the adder 19, a train of pulses with the current output frequency at i + 1-st period of the corresponding input frequency multiplied by K times, corrected by the signals of half the increment of the input frequency during the period ending and the current increment of the input signal, compensated by signals depending on the magnitude of the change in the first zvodnoy input signal.

Claims (1)

is the current time in the interval t.  and t are the beginning and end of the i + 1st period T. . .  A signal proportional to the first time derivative of the input signal is obtained by dividing the signal increment, proportional to the input frequency, by a time interval equal to the ending period. input frequency at which the increment is obtained.  The increment is obtained by subtracting two frequencies, formed by inversely proportional conversion of two adjacent periods of the input frequency with a coefficient of pryordionality, EQUAL K - device multiplication factor.  By introducing correction signals, one-half the increment of the instantaneous value of the input frequency over the time of the final period and the current increment of the input frequency proportional to the first time derivative of the input signal can be reduced in the known device. dynamic conversion error associated with a change in input signal.  The resulting signal,.  ; (v (. , M. t; v ,. “About 1.   1 O and 0 is only approximately proyorOnLen of the first derivative in time of the input signal, since the interval T-, on which the increment is obtained, can.  be large enough, especially in the low-frequency range, and its first derivative may change its value.  Therefore, expression (2) represents the value proportional to the average value of the first derivative with respect to time in the I-th period of the input signal, which must be attributed in time to the middle of the time interval T.  By the end of the t-rp period, in the case of a change in the PirvO derivative, a method ry shpka is formed, equal to half the increment of the first derivative during the 1st period.  In addition, in the prototype on the next time interval equal to.  + 1st period T. the signal obtained at the end of the i-th period, which is proportional to the first derivative, remains unchanged, whereas the derivative actually changes in this way.  The known device makes it possible to obtain good metric X and amphibiousness only for input signals that vary linearly or monotonously with time, which limits its scope.  For fast-moving dynamic processes, the value of the first derivative will vary between the two converters (within the period of the input frequency), therefore the output signal in the known device will have a dynamic error depending on the value of the second derivative of the input signal.  The aim of the invention is to reduce the dynamic error of the output signal.  .  -.  The goal is achieved by the fact that a pulse frequency multiplier, comprising a reference frequency generator, the output of which is connected to the input.  binary frequency multiplier and the first inputs of three frequency dividers, the output of the first one of which is connected to the first input of the pulse counter, the output of which is connected to the second input of the second frequency multiplier and the first output of the second input of the second frequency divider through the first code transfer unit the control unit, the second, third and fourth outputs of which are connected respectively to the second input of the first code transfer unit, the third input of the second frequency divider and the second input The third frequency splitter, the third input of which is connected to the output of the second code transfer unit, one input of which is connected to the first output of the second frequency splitter, and the second input to the fifth output of the control unit, the output of the binary frequency multiplier connected to the first input of the adder, the second input which is connected to the first output of the subtractor, one input of which is connected to the second output of the second frequency divider, the second input is connected to the first output of the third frequency divider, and the second output is connected via a trigger to the third th adder input directly to the first input of the fourth frequency divider, a second input coupled to a third output of the control unit, wherein the control inputs of the first and third divisors.  The leu frequency is connected to the bus for setting the multiplication factor, three frequency dividers, a binary frequency multiplier, a code transfer unit, two subtractions, additional triggers are entered.  The germ and the adder, the first input of which is connected to the first output of the first subtractor, the second input is connected to the output of the fourth frequency divider and the first input of the second subtractor, the second input of which is connected to the output of the fifth frequency divider, and the output of the second subtractor is connected to the first input of the sixth frequency divider and through an additional trigger - with the third input of the additional adder, the fourth input of which is connected to the output of the second binary frequency multiplier, the first input of which is connected to the output of the reference generator frequency, the second input is connected to the first, output of the control unit, the third input is connected to the output of the sixth frequency divider, one input of which is connected to the third input of the fourth frequency divider and the output of the first code transfer unit.  Moreover, the first input of the seventh frequency divider is connected to the output of the reference frequency generator, the second input through the third code transfer unit is connected to the second output of the third frequency divider, and the output of the seventh frequency divider through the third subtractor, the second input of which is connected to the first output of the third frequency divider, connected to the first input of the fifth frequency divider, the second input of which is connected to the output of the second code transfer unit, and the third input to the fourth output of the control unit, the output of the additional adder with common to the third input of the first binary multiplier is often s, and the fourth input of the adder is connected to the second output of the second frequency divider, the third inputs of the sixth and seventh frequency dividers are connected respectively to the third and sixth outputs of the control unit, the seventh output of which is connected to the second input of the third transfer unit code, and the input is connected to the input bus.  Each of the frequency dividers consists of sequentially connected memory registers, a transfer element code, and a pulse counter, the output of which is connected to the second input of the code transfer element.  FIG.  1 is a block diagram of the pulse frequency multiplier in FIG.  2 is a block diagram of a control unit.  The pulse frequency multiplier contains a reference frequency generator 1, a pulse counter 2, frequency dividers 3-9, each of which is made of a pulse counter 10 and a memory register 11 connected by bits through a code transmission element 12, binary multipliers 13 and 14 frequencies, tellers 15-17, adders 18 and 19, triggers 20 and 21, code transfer blocks 22-24 and control block 25.  The pulse frequency multiplier operates as follows.  In control unit 25, from each pulse of the sequence of the input frequency signal fx (t), at the outputs 26-32, control signals determine the sequence of operation of the frequency multiplier that arrive at the corresponding inputs 26-32 of the respective elements.  From the output of the generator 1, the pulses of the high reference frequency fj arrive at the counting inputs of the pulse counters of the frequency dividers 3, 4, 5, 7 and the binary frequency multipliers 13 and 14.  In divider 3, the reference frequency is divided by a constant coefficient K, which is a multiplier of the frequency multiplier, and recorded as a parallel code in memory register 11 of divider 3.  In dividers 4, 5 and 7, the reference frequency is divided into variable coefficients, written as a parallel code in memory registers after the end of each input frequency period.  Pulses, followed by a frequency: FQ from the output of divider 3, arrive at -.  the counting input of the pulse counter 2, where they are summed up in the time interval equal to the current period, of the input signal, and generated by giving the pulse counter 2 signals to the 2 bauble of the pulse counter 2 control signals from the block 25 after the arrival of each pulse of the input frequency.  At the outputs of the bits of the pulse counter 2 at the time of the survey, a code is formed, which is proportional to the finished i-th period of the input signal.  ; s -IS-. T.  This code before resetting the counter 2 pulses through the block 22 of code transfer by the signal at input 27 from block 25 is written into the register of 11 frequency dividers 4,6,8 and 9 frequencies previously released from the previous information on the signal at the inputs of block 25.  Before resetting the memory register 11, the 4 frequency divider, the NT code located in it is proportional to the previous i-1 period T is rewritten via the code transfer unit 23 by the signal at the input of the SOS, previously released by the signal at the inputs of the memory registers divider 5. and 8 frequencies.  Accordingly, before resetting the memory register of the frequency divider 5, its code N proportional to the i-2th TD period is rewritten by a signal at input 32 through the code transfer unit 24 to the frequency divider 7 previously released by a signal at input 31 of the memory register.  Thus, after the i-ro period of the input signal is completed, the NT code will be recorded in the memory registers of the dividers b and 9 of frequency 4, the NT code will be written to the frequency registers of the frequency dividers 5 and 8, the frequency divider 7 will be written to the memory register of the frequency divider. on the 4, 5, and 7 frequencies of the dividers, the frequencies will respectively be formed.  F, (t. ). - -K-yt 5; F, tt, -. ,) Kyt. ); (i-t t. e.  an increase in K times the frequency, corresponding to instantaneous values of the output frequency in the middle of periods 4 4-1 and T. d.  Pulses with frequencies Fx (t) and Fx (t4) from the outputs of dividers 4, 3 frequencies are fed to the inputs of the subtractor 15 / whose information output forms a sequence of impudates with a medium frequency, -; - 4 "x bfxt -ii) (proportional to increment the input signal during the i-ro period.  At the output of the subtractor 15, an increment sign signal Sing L Fy (t. ) corresponding to the sign of the first derivative of the input signal in the i-M period.  Accordingly, pulses with a frequency of Fv (t) and F (. j) From the outputs of the dividers 5 and 7, the frequencies are fed to the inputs of the subtractor 16, at the output of which a sequence of pulses is formed with a medium frequency. l-Fx (-,) - Fx (- abK x (4, bfx -J-Nf (i. , V is proportional to the increment of the input signal during the i-1-th period.  In the frequency divider b, the frequency dF (t), passed to its input from the output of the subtractor 15, is divided by the coefficient N-J-.  recorded in the memory register dividing wb after the end of the period.  At the output of the frequency divider 6, a sequence of pulses is formed with frequency.  t /, l uFx (i.  Miil-Ji:: ± zfci}. . l Lh (- m: -y -t: dt, -, proportional to the average value of the first derivative with respect to the time of the input signal in the 1st period.  In the frequency divider 8 frequency l.  F (t |, arriving at its input from output of reader 16, is divided by the coefficient NY, recorded in the register of memory of the case 8.  At the output of the frequency divider 8, a sequence of pulses is formed with a frequency.  ; ,,,. M -. C. , G is proportional to the average value of the first derivative with respect to the time of the input signal in the period.  Pulses with frequencies.  Fi (t) and F (t. a) from the outputs of the dividers b and 8 frequencies come the inputs of the subtractor 17, at the output of which a sequence of pulses is formed with a medium frequency,. ) -f; ft. ) -F; (t ,. ,) ) -f, 1t ,. , |. f) is proportional to the increment of the average value of the first derivative of the input signal over a period.  From the output of the subtractor 17, the frequency pulses AFx () are fed to the inputs of the divider 9 of the Irigger frequency 20.  A trigger 20 with a counting input performs the functions of a frequency divider by two, and at its output a sequence of pulses is formed with a frequency F (t) (tj arriving at the input of the adder 18.  To obtain a signal proportional to the second derivative of the input signal over time, t. e.  the rate of change of the first time derivative, a signal proportional to the increment of the average value of the first derivative is necessary, divided by the time interval over which this increment is received, t. e.  for the period ended.  The resulting signal will be proportional to the average value of the second time derivative of the input signal over the time interval of the ending period. When wauii unchanged or monotonous change in the second derivative over time, when the derivatives of higher orders are equal or close to zero, the received signal remains constant in the time interval of the next period of the input frequency and will correspond to the instantaneous value of the second derivative over time of the input signal in this interval.  The indicated character of the change in the input Signal, when the value of the first and second time derivatives is sufficient for its description, satisfies a wide class of dynamic systems in the field of measurement and control.  In the frequency divider 9, the frequency A Fj (t) is divided by the coefficient N-r recorded in the memory register of the divider.  At the output of the frequency divider 9, a sequence of pulses is formed with a frequency of fx).  V f.  , t ip i is proportional to the Average (The value of the second time-produced input signal in the i-th period.  . Pulses with frequency (t. ) are fed to the counting input of the control counter of the binary frequency multiplier 13, the first input of which receives the frequency fg from the generator output.  The capacity of the counters of binary multipliers 13 and 14 is the frequency and is set to K - device multiplication factor.  In the controlled counter of the binary multiplier 13, the frequency of the hour: t9ta FX (t) is integrated over the time interval i + 1-th period.  The current code in this counter will be equal to ВУ1 ГИ (,,. where t varies from t j to t.  At the output of the binary multiplier 13, a pulse sequence is formed with an average frequency -fefy H - x t H.  proportional to the current increment of the first derivative, depending on the rate of its change, t. e.  from the second derivative of the input signal over time.  The inputs of the adder 18 receive three pulse sequences pj (t) from the output of frequency divider 6, AFx {t4) from the output of trigger 20 and uFJ ((t) from the output of binary frequency multiplier 13.  These frequencies, depending on the signal of the increment sign, the input frequency D Fx () of the subtractor 15 coming from the output, are summed algebraically, and at the output of the adder 18 a sequence of pulses is formed with the current frequency at the i + 1-th period (,) tiaf ;; V . ) i if; 4. , K. . | {Mxi. M.  M. Jli. )}, 1-MLM-uMLbll-U - t Tg-vJ 1 is proportional to the current value of the first time derivative of the input signal, corrected by signals compensating the methodological and dynamic errors.  Impulses. with frequency F. (T.  ) from the output of the adder 18 —access to the counting input of the control counter of the binary multiply.  bodies 14, the first input of which receives the reference frequency from the generator output -1.  At the exit . binary multiplier 14, a pulse train is formed with the average frequency Ayt) (T. ,),) - t iuf; {t. , ). i5.  -ti is proportional to the current value of the input signal increment in time, compensated for the values of methodical and dynamic errors.  The inputs of the adder 19 receives three sequences of pulses F (t. i) from the output of the divider 4 frequencies, &amp; F, ((t) - output of the binary multiplier 14 frequency and bsJJEJJc output trigger 21.  These frequencies depend on the sign of the sign of the increment of the input frequency, l Fx- (t. ;), from the output of the subtractor 15, are summed algebraically, and at the output of the adder 19 a sequence of pulses is formed with the current output frequency in the i + 1 st period V, 4. ).   . a corresponding multiplied K input frequency, corrected by signals of half the input frequency increment over the time of the ending period and current input increment compensated by signals depending on the magnitude of the change in the first derivative of the input signal.  Claim 1.  A pulse frequency multiplier containing a reference frequency generator, the output of which is connected to the input of the binary frequency multiplier and the first inputs of three partial frequency dividers, the output of the first of which is connected to the first input of the pulse counter, the output of which is connected to the second input of the second frequency divider through the first code transfer unit, and the second input of the pulse counter is connected to the second input of the binary frequency multiplier and the first output of the control unit, the second, third and fourth outputs of which are connected respectively with the second input of the first code transfer unit, the third input of the second frequency divider and the second input of the third frequency divider, the third input of which is connected to the output of the second code transfer unit, one input of which is connected to the first output of the second frequency divider, and the second input to the fifth WELHODE control unit, the output of the binary frequency multiplier is connected to the first input of the adder, the second input of which is connected to the first output of the expander, one input of which is connected to the second output of the second frequency converter, the second input one connected to the first output of the third frequency divider, and the second output connected via a trigger to the third input of the adder and directly to the first input of the fourth frequency divider, the second input of which is connected to the third output of the control unit, while the control inputs of the first and third frequency dividers are connected to a multiplication factor setting bus, characterized in that, in order to reduce the dynamic error of the output signal, three frequency dividers, a binary frequency multiplier, a code transfer unit, two subtractors, an additional trigger and an adder, the first input of which is connected to the first output of the first subtractor, the second input is connected to the output of the fourth frequency divider and the first input of the second subtractor, the second input of which is connected to the output of the fifth frequency splitter. and the output of the second subtractor is connected to the first input of the sixth frequency divider and through an additional trigger with the third input of the additional adder, the fourth input of which