SU771674A1 - Computing device for solving differential equations - Google Patents

Description

 . 1, the invention relates to the field of computing technology and can be used to solve partial differential equations. A combined computer is known, which consists of two arithmetic units connected by a general operational storage device, one of which is integrated integrating 1. The disadvantage of such a device is a relatively low speed, due to the fact that both computing units have a consistent structure. Of the known devices, the closest in technical solution is a combined computing system 2 containing a general-purpose digital computer whose information output through a buffer memory block, the first converter, a switch block is connected to the inputs of the first decision blocks connected by information inputs and outputs between each other, control inputs and outputs to the control device, information outputs through the block buffer. The NOY memory and the second converter are connected to the input of the digital computer, the information output of which is also connected to the buffer address counter liami, the address register of the boundary decision blocks, the information sign register and the local control unit that has two-way communication with the digital computer and the control device and the output connected to the control input of the register, a sign of the information connected to the decoder of the sign of information connected to the input of the switch unit, to the control input of the register of the address of the boundary decision blocks, with the address decoder of the boundary decision blocks, connected to the address inputs of the decision blocks, to the control input of the buffer memory address counter, connected to the address decoder of the buffer memory, connected to the input of the buffer memory block, to the control input of the switch block and to the input of the buffer memory block. The known device is intended for solving differential equations of partial differential equations, represented by the grid method in the form of a system of finite-difference equations of the form, and {,). H-ag-1 - {, nL (1) which in the matrix record has the form (2) where A is the coefficient matrix with components 3. Y is the solution vector with components VJ-- the vector of free members with components f- .. The decisive blocks of the known device implement solution (2) by the iterative method, where 77. A. + i;) failure to solve at the kth iteration, -TfC iterative parameter. The disadvantage is the relatively low speed of the computing system, which took place for stationary iterative methods (j const does not depend on k) due to slow convergence of iterations, as well as for non-stationary, self-adjusting in the process of solving for optimal convergence, iterative methods, in particular method of minimal bursts, in which (4) tl (An i due to the time spent on the transfer of intermediate results from solving their blocks to a digital computer for computation by relatively slow programmed pa The meter TC provides optimally fast convergence of the iteration. This disadvantage is associated with the absence of blocks and links in the known device that allow the acceleration of the convergence of iterations by solving (4) the iteration parameter m; without a significant increase in the time interval Meatfly to two neighboring iterations of the computing system. The aim of the invention is to increase speed. This goal is achieved by the fact that the first group is decisive in a computer system for solving differential equations containing a digital computer. blocks, a control unit, a buffer memory, a word format converter, an addressing device, an information sign maker, the information output of a digital computer connected to the first information inputs of the buffer memory of an addressing device, a sign maker of information and a two-way control unit with a digital computer; control inputs, word format converter, buffer memory. the addressing device of the information sign generator is connected to the first control output of the control device, the second control output of which is connected to the first control inputs of decision blocks of the first group, the second control to the first information inputs connected to the first output of the sign generator of information and the word format converter , the second output and the input of which are connected respectively to the input of the digital computer and the output of the buffer memory, the address input of which connected to the output of the addressing device, the first information output of the i-ro decision block of the first group (i T p) is connected to the second information inputs of the (i-1) -th and (i + l) -ro solver blocks and to the second information input of the buffer memory, the second group of decision blocks, two adders and a division block are entered, the first and second information outputs and the first information inputs and, the first and second control inputs of the decision: blocks of the second group are connected, respectively, with the inputs of the first and second adders, and the output of the converter The word format, the information sign maker and the second control output of the device, the first and second inputs and the output of the division unit are connected respectively to the outputs of the first and second adders and the third information inputs of the decision blocks of the first group; the second information output of the i-ro decision block of the first group is connected to the second information inputs of the (i-1) -th, i-ro and (i + l) -ro decision blocks of the second group, the output of the second adder is connected to the second information in the control unit . The presence in the computational system of second decisive blocks, the first and second adders, the division block allows to increase the speed of the device (to reduce the time to solve the problem) by adjusting the iterative process implemented by the decisive blocks to optimally fast convergence without transferring the intermediate data necessary for calculating Hz from decision blocks in the digital computer and implementation of the calculation of the iteration parameter g, by high-speed hardware. FIG. 1 shows a block diagram of a computer system for solving differential equations; in fig. 2 and FIG. 3 shows the schemes of decision blocks of the first and second groups. . The system contains a Shch1grame computer 1, connected by an information output-. course with the inputs of the control device 2, the imaging feature of information 3, the device address1 4, with the first information

the input of the buffer memory 5, the address input of which is connected to the output of the address1dai 4 device, and the control input, as well as the control inputs of the word format converter 6, the addressing device 4 and the information sign forming unit 3 are connected to the output of the control device 2 connected by the first control input and output with digital computer 1, second control input and output - with first control input and output of control device 2 connected by a second control output to first control inputs of decisive blocks 7i - 7j of the first group upy and decisive blocks Sj - 8y, of the second group, connected by control inputs with inputs of the information sign forming unit 3 and connected by the first (blocks 7i - 7, and blocks 8i - 8,) information inputs; to the second output there is a transducer 6, connected to the first output with the digital computer 1, and the information input to the output of the buffer memory 5. The wiring blocks are 1y (connected to each other by the second information inputs and the first information outputs connected to the second information input of the buffer memory 5. Each i- 8 deciding block connected by the first information inputs to the second information output of each i-ro and connected to the i-th decisive blocks 7-, .. l. connected by the first and second information output to the input of the first 9 and second 0 adder connected by an output to the second control input of the control device 2 and to the first input of the division unit 11 connected by the second input to the output of the first adder 9, and output to the third information inputs of the first decision blocks 7i - 7ts.

The block diagram of the first decision block 7 Dfig. 2) contains an input unit 12 connected to the inputs of the first register 13, second register 14, multiplication unit 15 connected by other inputs to the outputs of the first 13 and second 14 register, and output to the input of the first adder 16 connected by the output to the input of the second adder 17 connected by another input and output with the output and input of the first register 13. The inputs 18-22 of the multiplication node are in order of listing the first, second, third information and first and second control inputs of the decisive unit 1. The output 23 of the first register 13 and the output 24 of the first adder 16 are, respectively, the first and second information output of the decisive unit 7.

The block diagram of the decision block 8 (Fig. 3} contains the input input 25, connected to the inputs of the first 26 and July 27 multiplication streets, the other input of which is connected to the output of the adder 28, connected to the output of the first multiplication node 26. Inputs 29- The 32 nodes of input 25 are in the order of listing the first and second information, the first and second control inputs of the decision block 8. The outputs 33, 34 are respectively the first M and the second information outputs of the deciding block 8.J.

The buffer memory 5 consists of n registers and is designed to receive (output) information from (c) DVR 1 sequentially according to words in parallel according to the bits of transmission of information to decisive blocks 7i - 7y ,, 8i - 8y, and from decisive blocks 7i -7 ), in parallel, according to words, sequentially, by bits, according to the signals of control device 2, the selection of the required register is carried out with the help of device 4,

Converter 6 serves to convert the format of the information word DVM 1 into the format of the information word decisive blocks 7i - 7vi, 81 -, Svi (and vice versa) during data transfer between DVM 1 and decisive blocks.

The control unit 2 synchronizes and controls the operation of all the blocks that communicate between the digital computer 1 and the decisive blocks 7i-7i, 8, -8.

The decision block is designed to calculate the component of the solution vector y at each of the second iteration of the operation of the computational

systems that

Decision block 8. (designed to calculate the values proportional to the differences of 771 values proportional to the values At (At) included in the formula (4) for determining the optimal iteration parameter t.

The division block I serves for executing the value of the optimal iterative parameter m as a quotient of dividing the sum received at the n-input adder 9 by the sum obtained at the n-input with tmmator 10.

In the process of calculating the solution. synchronization and control of decision blocks 7i - 7yjn8j - BVI implements the device

control 2, forlating start and stop signals.

In the decision block, the input node 12 is designed to enter the source data before starting the decision in registers 13, 14 (zero

Claims (2)

iteration of the UR and the free term) and into the multiplication node 15 (the resolution of the difference in equation (1) using the information generator 3, for connecting the integral decisive blocks - 7, for inputting into the multiplication node 15) 1 and the iteration parameter. The first register 13 serves for storing and issuing at each iteration the solution of v. The second register 14 is intended for storing and issuing a free member The multiplying node 15 serves to calculate the products of the decisions of the coefficient on the coefficients a and the value of the iteration parameter rj. The first adder 16 is used to calculate the value by summing the products obtained in the multiplication node 15 / see formulas (1), (3) /. The second adder 17 serves to calculate the solution y by summing the values y and received from the outputs of the first register 13 and the first adder 16 / see formula (3) /. In the second decision block, input node 25 is designed to enter information signs into the first node multiplying 26 of coefficients a of difference equation (1) using shaper 3 before starting solving the problem and connecting outputs of 24 decision blocks 7u {,, 7 ,, to the inputs of the first and a second multiplying units 26 and 27 in the process of problem solving. The first multiplication node 26 serves to calculate the products of quantities proportional to the inequality of m and the coefficients. Adder 28 is designed to calculate the value of m (A.r) by summing up the 26 products obtained at the multiplication node. The second multiplication node 27 serves to obtain the products at the outputs 33, 34 proportional to the values of n1 | Ar | and (), respectively. The computer system for solving differential equations occurs; in the following way. From DVM 1, sequentially, according to words and in parallel, by bits using devices 4 in n registers of the buffer memory block 5, information is read, which is then parallel to words and sequentially by bits, changing its format on the converter 6 accordingly, goes to the first information inputs 18 of decision blocks 7i-7c and of the second information inputs of 30 decision blocks Sj-8у, and depending on the sign of information received from the generator 3 to the second control inputs 22, 32 of decision blocks 7i-7y, Sj - recorded in re 13, 14 (y, ip-j) and into the multiplication node 15 (coefficients a-f) of decision blocks 7i - and into the first smart node 26 (coefficients a) of decision blocks 8, - By ,. After entering the initial information into the decisive blocks 7i - 7y, 81 - 8, 7 "control unit 2, the s | | The start-up, which comes along the first control, 1 and the inputs 21, 31, to the decision blocks 7j - 7у, 8 - 8 c, with the help of which the differential equation is solved, represented in the form of (1) by the iterative method (3), (4) . In addition, at each iteration of the operation of the device in the first decision block 7, the inputs of the multiplication unit 15 are received from the outputs of the first 13 and second 14 registers, the solution found at the previous iteration and the free term from the output of the input node 12 of the value U. 23 neighboring decision blocks coming from the first information outlets -f-- | connected to the second information input of the 19 d. one decisive block, and the value of the optimal iterative parameter G (coming from the output of the division block I to the third information input 20 of this decisive block. In the last repetitive blocks 7i, 7, the boundary conditions of the VO.UI enters from the buffer memory 5 through the converter 6 to the first information input 18 of the corresponding input node 12. From the output of the multiplication unit 15, the resulting products,., go to the first adder 16, where they are summed up, according to formulas (1), (3) , value to IK, n coming to the input of the second adder 17, to the other input of which the value of y comes from the start of the first register (13. The received amount is the solution found on the kth iteration and is written to the first register 13. The values from the second information output 24 decision blocks, VH, arrive at the first information inputs 29 of the decision block 8 :, and from the input node input 25 values, t i, arrive at the input of the first multiplication node 26, where they are multiplied by the coefficients aa.,. The obtained products are summed on adder 28, according to (1), (2) the value that enters the input of the second multiplier of node 27, to the other input of which a value comes from the output of input node 25 .. The second multiplier 27 forms the first 33 and second 34 and informational outputs of the second decision block 8 works, (Gk.), Which from the outputs of all the second decision blocks 8 | - 8c are received, respectively, at the inputs of the first 9 and second 1 LCH 10 adders of the computing system, from the output of which the obtained sums go to the inputs of the division unit, which forms the value of the optimal iteration parameter T found at the k-th output iterations, which then goes to decisive 7-7. The iterations of the computing system continue until a stop signal is generated in control device 2 when the end criterion for the iteration process is completed, which is the smallness of the value () coming from the output of the second adder 10 to the second control input of the control unit 2. The introduction into the computing system of the second decision blocks Sj - 8c, the first adder 9, the second adder 10 and the division block 11 distinguish the computing system for solving differential equations from the prototype, as it allows to increase the speed by implementing the self-adjusting in the process of solving the optimal convergence of the iterative method of the minimum bounds, excluding the inherent costs of the prototype remeni to transfer from. the first decision blocks in the digital computer of intermediate results of development at each iteration, necessary for calculating the iteration parameter, which is implemented in the proposed computer system by high-speed hardware, in the prototype, however, only by a slower programmatic path. For m iterations performed by the computing system when solving a differential equation, the time spent on transferring data from the decision blocks to the digital computer and the iterative parameter from the digital computer to the crucial blocks excluded by the invention for the prototype is m (nH) t, where t is the transmission time one information word, and m, n in real systems, there are quite large numbers, which determines the economic effect of the device. A computer system for solving differential equations comprising a digital computer, a first group of decision blocks, a control device, a buffer memory, a word format converter, an addressing device, an information sign maker, and the information output of the digital computer is connected to the first information inputs of the buffer computer. memory, addressing device, information sign maker, and control unit, connected by one-way two-way communication with digital by the computer, the control inputs of the word format converter, the buffer memory, the addressing device, the information feature generator are connected to the first control output of the control device, the second control output of which is connected to the first control inputs of the decisive blocks of the first group, the second control and the first information inputs connected respectively to the first output of the information sign formatter and the word format converter, the second output and input of which are connected to This information is connected to the input of the digital computer and the output of the buffer memory whose address input is connected to the output of the addressing device, the first information output of the i-ro decision block of the first group (i 1-п) is connected to the second information input (-T) and (iH) -ro decision blocks and with a second information input of the buffer memory, characterized in that, for the purpose of higher (w speed, it contains a second group of decision blocks, two adders and a division block, with the first and second information outputs and first information inputs and first The second and second control inputs of the second block second block are connected respectively to the inputs of the first and second adders, the output of the word format conversion, the information sign former and the second control output of the control unit, the first and second inputs and the output of the divider are respectively connected to the outputs of the first and second adders and third information inputs of the decision blocks of the first group of the second information output of the i-ro decision block, the first group is connected to the second and information inputs (i-1) -d , .I-ro and (i + l) -ro critical blocks of the second group, the second adder output is connected to a second data input control ustroysta. Sources of information taken into account during the examination 1. USSR author's certificate No. 155668, cl. G 06 J L / 02, 1962. 2. USSR author's certificate number 524490, cl. G 06 J 3/00, 1973. / fl / 520 25 25 30 J / 32 ig.2