SU769619A1 - Device for shaping address signals - Google Patents

Description

changes in the contents and register of fixing the results of logical operations, the first inputs of which are connected to the first output of the control unit, the second inputs, excluding the register of fixing the results of logical operations, to the output of the accumulator. The outputs of the register of the address of the field of the operative memory, the first and second registers of the address of the initial border of the array, the register of the length of the array and the register of the address of the final boundary of the array are connected to the inputs of the arithmetic unit from the fifth to the ninth. The output of the memory length register is connected to the control output of the device. The output of the register of change of contents is connected to the second input of the control unit, the third input of which is connected to the first output of the register of fixing the results of logical operations, the second input and output of which are connected respectively to the fourth output of the arithmetic unit and control output buses.

The drawing shows a diagram of an apparatus for generating address signals.

The device contains a drive 1, which can be used as a super-operative memory, address register field operative memory 2, the first register of the address of the initial border of the array 3, register of the length of the array 4, the second register of the address of the initial border of the array 5, register of the address of the end border of the array 6, the memory field length register 7, the register for changing the content 8, the arithmetic unit 9, the buffer register 10, the register of fixing the results of logical operations AND, the output address register 12, the address output buses 13 the devices controlling the output buses 14 of the device, the control unit 16 and the input buses 16 of the device.

The first inputs of accumulator 1, blocks 9 and 15 are connected to buses 16. The second inputs of accumulator 1 and block 9, as well as the first inputs of registers 10 and 12 are connected to the first output of block 15. The first and second outputs of block 9 are connected respectively to the second inputs of registers 10 and 12. The outputs of register 12 are connected respectively to the third input of block 9 and buses 13. You register 10 codes are connected respectively to the third input of register 12 and the fourth input of block 9. The second output of block 15 and the third output of block 9 are connected to buses 14.

The first inputs of registers 2-8 are connected to the first output of block 15, the second inputs, excluding the register I, to the output of accumulator 1. The outputs of registers 2-6 are connected by the inputs of block 9 (from fifth to ninth). The output of the register 7 is connected to the bus 14. The output of the register 8 is connected to the second input of the block 15, the third input of which is connected to the first output of the register I,

the second input and output of which are connected respectively to the fourth output of block 9 and tires 14.

The device works as follows.

Bus 16 receives the number of the external address, the address of the operand on the external memory and the length of the operand. The control unit 15 reads the information from the accumulator 1 to the registers 2-8 in the first clock cycle and sets the register to zero. In the second clock cycle, the register 4 and the operand address from the buses 16 are input to the input of the arithmetic unit 9, and it is determined that the address of the operand is less than the address of the array's final limit, the result is sent to the first bit of register 11. In the third clock cycle, the input of the arithmetic unit 9 is the address of the bus 16 and the contents of register 3, and it is determined that the address of the operand is greater than the initial address An array array, the result is sent to the second bit of register 11. In the fourth clock cycle, the input of the arithmetic unit 9 is supplied with the contents of register 6 and the address of the operand from the bus 16, and it is established that the address of the operand is less than the address of the array's final boundary in the outer address field, the result is sent to the third bit of register 11. In the fifth cycle, the address of the operand from the busses 16 and the contents of register 5 are fed to the input of the arithmetic unit 9, and it is determined that the address of the operand is greater than the address of the initial border of the array of the external address field; and sent to the fourth bit of the register I. In the sixth cycle, the contents of register 6 are fed to the input of the arithmetic unit 9, the address of the operand that comes from buses 16 is subtracted from it, the result is sent to the register 10. In the seventh cycle, the contents are fed to the input of the arithmetic unit 9 register 10, it is established that it is greater than or equal to the length of the operand, the result is sent to the fifth digit of the register I. In the eighth cycle, the input of the arithmetic unit 9 is the address of the operand from the busses 16, the contents of register 5 are subtracted from it, the result is sent are in the register 10. In the ninth cycle zasylaets the arithmetic unit 9 the contents of register 10, to it is added the contents of register 2, the result is placed into register 12.

If the address of the operand is not in the external address field, the processor (not shown) reads the necessary information in the address field and corrects the addresses of the initial and final array boundaries in the address field in drive 1.

Claims (2)

If the processor detects that the register bit 8 is one, then the information from the external address field is written to the external media at the address of registers 5 and 6 before reading. When performing an action, when changing the contents of the external address zero, a single value of the sign of the content change is set to 16 by the block control 15 in the accumulator 1. The address change during the operation is performed in the arithmetic unit 9 by adding to the address in the register 12 a value that is received via buses 16, the result The AT is sent to register 10, and from it to register 12. When commands are addressed to memory addresses, the execution address is generated by summing the base address read from drive 1 to register 2 and the index address supplied by buses 16. The result is put into register 12. When changing the assignment of the external address, information about the new assignment by the processor is sent over the tires 16 and recorded under the control of unit 15 to the accumulator 1. The invention allows to significantly expand the field of application of the device due to reducing the number of commands, regulated input / output information, and allowing arbitrary access to arrays on external storage devices. The invention The device for generating address signals, including its tip, buffer register, address output register, arithmetic unit and control unit, the first inputs of the accumulator, the control unit and the arithmetic unit are connected to the input buses of the device, the second inputs of the accumulator and the arithmetic unit, and also the first inputs of the buffer register and the output register of the address are connected to the first output of the control unit, the first and second outputs of the arithmetic unit are connected respectively to the second inputs b The address register, the outputs of which are connected to the third input of the arithmetic unit and the device’s address output buses, the outputs of the buffer register are connected to the third input of the output address register and the fourth input of the arithmetic unit, the second output of the control unit and the third output of the arithmetic unit are connected to controlling the output tires of the device, distinguished by the fact that, in order to expand the field of application of the device by reducing the number of commands, amentplus, their input-output information and the provision of arbitrary access to arrays on external storage devices, it contains the register of the address of the field of the operative memory, the first and second registers of the address of the initial border of the array, the register of the array length, the register of the address of the final border of the array, the register of the length the zero of the operating memory, the register of the sign of changing the content and the register of fixing the results of logical operations, the first inputs of which are connected to the first output of the control unit, the second inputs, excluding the reg A record of the results of logical operations, - to the output of the accumulator, the outputs of the register of the address of the field of the operative memory, the first and second registers of the address of the initial border of the array, the register of the length of the array and the register of the address of the final border of the array are connected to the inputs of the arithmetic unit, the output of the memory field length regnstra is connected to the control output device buses, the output of the register of the content change indicator is connected to the second input of the control unit, the third input of which is connected to the first results in the output fixation logical operations register, the second input and output of which are respectively connected to the fourth output of the arithmetic unit and the control S., imivyhodnymi tires. Sources of information taken into account in the examination 1. The author's certificate of the USSR 338902, cl. G 06F 9/20, 1969. 2. US patent number 3818460, cl. 340-172.5, 1974 (prototype).