SU754480A1 - Storage - Google Patents

Description

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The invention can be used as a transmission buffer in telemetry and automated control systems.

The memory is known, which contains two (several) identical information transfer channels (groups of main registers), groups of elements I, control circuits and switches by the number of channels, as well as input and output registers ₁₀ Information transit time

from the input to the output of the device is small. However, all these channels are equivalent and therefore priority information transmission is not provided for them. _]five

The closest technical solution to the invention is. The memory, which contains the digitally connected registers with information and marker bits, the rewrite control cells ₂₀ and the coincidence of the number of registers and the source of clock signals ^ 2 ^.

The disadvantage of such a device is that the information requiring pri2

priority transmission is transmitted in general order. At the same time, its fast (immediate) acquisition and analysis by the receiving complex is excluded.

The aim of the invention is to increase the speed of the device.

This goal is achieved by the fact that in the memory containing the main information transmission channel, the outputs of which are connected to the inputs of the OR element, the output register, the inputs of which are connected to the outputs of the OR element, the outputs of which are the device outputs, the block of buffer memory of the priority information are entered the transfer, the prohibition element and the control unit, the input of which is connected to the control output of the output register, the first output is connected to the control input of the block of buffer memory priority information, the second to the control input of the main information transmission channel, and its control inputs are connected respectively to the output 754480

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the prohibition element, the first input of the prohibition element and the output of the pulse inhibitor shaper of the priority transmission, one of whose input is connected to the information output of the main information transmission channel, the other inputs are connected to the outputs of the buffer memory block of the priority information, the control and information inputs of which are device inputs , the information input is connected to the information input of the main channel, information transfer, and the outputs of the block of buffer memory of priority information are connected to the corresponding inputs of the OR element and the second input of the prohibition element.

The functional diagram of the memory is shown in the drawing, where the main information transmission channel 1, the element OR 2, the output register 3, the information bits 4, the message message bits 5, the rewriting cell 6 and the input valve 7, the buffer memory block of the priority information 8, the request pulse driver are indicated priority transmission 9, prohibition element 10, control unit 11, control trigger 12, valves 13, 14, information input 15, first 16 and second 17 control inputs, information output 18, service output 19, single outputs of the buffer pa unit yati priority information 20, the control inputs and outputs 21, 22, first and second control inputs 23 of the control unit.

The device works as follows.

The current messages go to input 15, from which the closed valve 7 of the buffer memory block of priority information 8 and to the input of the main information transmission channel I are sent. Therefore, the registers of channel 1 are filled with current messages that are automatically promoted to its output.

If register 3 is free, then a signal is generated at its output 21, which is fed to the input of the control unit 11 and through its open valve 14 to the input 21 of channel 1. Therefore, the message about the outputs 18 and 19 of channel 1 through the OR element 2 goes to register 3, where is written in the information bits 4, and the sign of the message is fed to the input of discharge 5, which is transferred. At the same time, a signal is taken from its output 21, and a signal is formed on its

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a single exit 20 from which postug ·

It goes to the input of rewriting cell 6. When a clock signal arrives at input 17 of this cell, a rewrite signal is generated at its output, · / which rewrites the message from register 3 to outputs 18 and 19 of the device. In this case, the discharge of the indication of the message is transferred, the signal from the output 20 is removed and formed

Yu at its output 21. In this case, the following message is received at the input of register 3.

In the case when a message is sent to input 15 that requires priority transmission, a signal is sent to control input 16 and valve 7 is opened. The message arrives at the inputs of the first register of memory block 8 and is stored in its bits 4, and the sign of the message

20 enters the category 5, which is transferred. In this case, at its single output 20, a signal is generated that arrives at the first input of rewriting cell 6. If the next register is free, then from its output 21, the second input of cell 6 also receives a signal. When a clock signal arrives at the third input 17 of cell 6, a signal is generated at its output that rewrites the message from the first register to the second. In this case, the signals are removed from the output 20. the first register and from the output 21 of the second register, and a signal is generated at its output 20. Thus, the message

35 advances automatically into the last register of the memory block 8.

The signals from the single outputs of 20 bits 5 signs of the message block.

4 _{0 of the} memory 8 are also fed to the inputs of the pulse shaper request 9, which when the input of the sign of the end of the transfer of the current group of messages from channel 1 generates a signal

45 request for priority transmission of messages from memory 8. This signal from the output 23 of the pulse shaper request 9 is fed to the input of the element of the prohibition 10 and closes it, as well as

₅₀ to the input 23 of the trigger 12 of the control unit 11, which is thrown. This closes the valve 14, and the valve 13 is opened. The signals from the output 21 of the register 3 pass through the valve 13

₅₅ of the control unit 11 to the input 21 of the cell 6 of the last register of the memory block 8. When a cell arrives at the input 17 of the cell 6, a clock signal _H and its output

a rewrite signal is generated which

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transmits a message from the last register to the output of the memory block 8. The message from the outputs 18 and 19 of the memory block 8 through the element OR 2 and the register 3 enters the outputs 18 and 19 of the device, bypassing channel 1.

Subsequent messages also arrive at the output of the device from memory block 8 until it is completely free. When the memory block 8 is released, the signals from its outputs 20 and from the output 23 of the pulse driver 7 are removed, and the prohibition element 10 opens. The sign of the last. Priority, messages from the output 19 of the memory block 8 through the prohibition element 10 is fed to the input 22 of the trigger 12 of the control unit 11, which is thrown. When this valve 13 is closed, and the valve 14 is opened, and the signals from the output 21 of the register 3 through the valve 14 of the control unit 11. are fed to the input 21 of channel 1, while the output of the device receives messages from channel 1. They also arrive at the input 18 of the pulse shaper request 9, which analyzes the current messages, as well as signals arriving at its inputs 20.

The proposed device provides fast transmission of priority information, since the main information transmission channel accumulates tens and hundreds of messages, and the block of buffer memory can contain only a few sequential registers that form the transmission channel of priority messages.

In addition, the device provides priority information transfer, both in single and in group transmission of messages, which increases the efficiency of its work.

Claims (1)

A memory device containing a primary information transmission channel. the outputs of which are connected to the inputs the OR element, output register, inputs which are connected to the outputs of the element OR, the outputs of which are outputs ₅ of the device, characterized by the fact that in order to increase the speed of the device, a block of buffer memory of priority information is entered into it, the request shaper Yu priority transmission, a prohibition element and a control unit whose input is connected to the control output of the output register, the first output connected to the control input of the buffer memory block of priority information, the second to the control input of the main information channel, and its control inputs are connected respectively to the output element of the prohibition, the first input 20 prohibition elements and to the output of the pulse shaper of the priority transmission request, one of the inputs of which is connected to the information output of the main information transmission channel, others 25 inputs are connected to the outputs of the buffer memory block of priority information, the control and information inputs of which are device inputs, with the information input _{3θ of} keys to the information input of the main information transmission channel, and the outputs of the buffer memory block of priority information connected to the corresponding inputs of the OR element and the second input element of the ban.