SU752816A1 - Pulse counter with controllable recounting factor - Google Patents

Description

(54) CONTROLLER IMPULSE COUNTER The invention relates to the derivation and impulse technology and can be used to construct counters with a controlled conversion factor. A counter with a controllable recalculation coefficient is known, containing N tritheres, five EHL / gents and NOT keys, which specify the recalculation coefficient ij. HeAOCTBTKCfM of this device is with its complexity. Also known is a counter with a controlled recalculation coefficient containing N counting triggers, N control buses, an input bus, a NOT element, and an AND-OR-NOT element with N +1 AND structure, the inverse output of each of the counting triggers is connected to the counting input of the next counting Tpirrrepa and with the first input of the corresponding structure AND of the AND-OR-NOT element, the second input of which is connected to the corresponding control bus, the input of the N structure AND the AND-OR-NOT interface is connected to the input bus and with the counting input of the first counting trigger, the RESET output by COEFFECTIENT The element AND-OR-NOT is connected through the element NOT to the inputs of the installation in O of the flip-flops 2. A disadvantage of this device is that the pulse of the installation of the counting triggers in the O has a small dielectricity and, in the case of a large variation of the parameters of the electrons, may be insufficient to reset in O all countable, t-riggers, that is, such a device has a low functional reliability. The purpose of the invention is to increase the functional reliability. To achieve this goal in terms of pulse counting with a controlled coefficient (} conversion count, 1 1 N counting triggers, N control buses, an input bus, a NOT element, and an AND-OR-NOT element with N +1 structure AND, the inverse output of each from the counting triggers connected to the counting input of the subsequent) counting trigger and to the first input of the corresponding structure AND AND OR-NOT, the second input of which is connected to the appropriate: tweaking bus control, input-K +1 of the structure AND AND-AND-NO connected to the input bus and with the counting input of the first counting three ger - -element output AND-OR-NO element is connected via elements, with the cop NOT installation in entrances Countable triggers Nyo element output is connected to third inputs of first AND-element H strultur AND-OR-NO. FIG. 1 shows a structural c & ma counter; in fig. 2 - the first bit size of the counter; Fig. 3 of the second and remaining bits of the counter. The counter contains four counting triggers 1-4, sn vieHT NOT 5, element AND-OR-NOT 6 with structures AND 6D, 6.2, 8.3, 6.4, b.5p input 7, output bus 8, mifflbi 9-12 control. The inverse outputs of counting triggers 1-4 are connected respectively with the counting inputs of counting triggers and with the first inputs of structures AND 6.2-6.5 of the AND-OR-HE 6 element, the second inputs of which are connected respectively to the control buses 9-12, and the third inputs with output bus 8, with the output of the element NOT 5 and from the input of the installation in О of the counting, triggers 1-4, the input bus 7 is connected to the counting input of the counting trigger 1 and with the inputs of the structure AND 6-1 of the AND-OR-HE 6 element, the output of which is connected to the input element HE 5, the device operates as follows. If at the initial moment there is a high potential on control buses 9 and 11 and a low potential on tires 10 and 12, and before applying a positive counter pulse to bus 7, all counting triggers are in a zero state with high potentials at zero outputs, at the output of element 6 - low potential, and at the input of element 5 - high potential. The first impulse goes to the bus 7 of the counter, then to the counting input of the first counting trigger 1 and sets it to state 1, and also arriving at the input of structure AND 6.1 of the AND-OR-NOT element 6, causes a low potential at its output, which does not change the state of the counting triggers. The second input pulse sets the counting trigger to zero, and the counting trigger 2 to one, etc. When the fifth pulse counter arrives on the bus 7, the counting triggers 2 are set to zero, and the counting triggers 1 and 3 are in the field. After installation in 1 counting trigger 1, at one of the inputs of 1 CHZ structure AND 6.2, 6.3, 6.4, 6.5 of the element AND OR-NO 6 - low potential, the input of structure 6.1 is high potential-gal and at the output of the AND-OR element - NOT 6 - low gtotenstl. After the termination of the 5th amplitude on bus 7, at the output of element 6, a high potential appears, causing a low potential at the output of element 5, which zeroes all of the counting triggers and blocks the structures AND 6.26, 5 of ep. 6, the arrival of the sixth pulse on bus 7, the output of element 6 appears to be low potential, and the output of element 5 is high, while the counting trigger 1 goes to state 1. Upon receipt of subsequent impulses on bus 7, the device functions similarly. The output impulse of the device on bus 8 is equal to the duration of the impulse to install in O of the counting triggers 1-4 at the output of element 5 and is determined by the length of the negative phase of the input signal on bus 7, which can always be chosen sufficient for reliable installation in O of the counting triggers. The output of the element 5 must be connected in the counting trigger 1 only to the output trigger, i.e. the first trigger of the counter must be made according to FIG. 3, which simplifies the scheme of the counter when the NEG1 is executed in the form of a single integral system. In a similar way, a counter-transfer counter is built. The formula of the invention Pulse counter with controllable conversion factor, containing N counting triggers, W control buses, and a modular pin, the element NOT and the element ILYE NOT with the N-AND structure, the loop output of each of the counting triggers is connected to the counting input of the subsequent counting trigger and with the first input of the corresponding structure AND AND-OR-NOT element, the second input of which is connected to the corresponding control bus, yhad N +1 of the structure AND element AND-OR-NOT is connected to the input bus and with the counting input of the first counting trigger, output ele tlenta. The AND-OR-NN is connected to the non-standard inputs with the installation inputs to the control room of the TpirrrepOB, which is functional reliability, the output of the element is NOT connected to the third inputs of the first N structures AND AND-OR-NOT elements.

Sources of .tcpl. Formation taken into account in peer review

No. 517164. KP, N. OZ K 23/26, 1976.

2. USSR author's certificate 5 No. 456366, K7I. N OZ K 21/36, 1975 (prototype).

FIG. 2

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Claims (2)

Claim A pulse counter with a controlled conversion factor, containing N counting triggers, N control buses, a suitable bus, an element NOT and an element: Y-ILY-NOT with N +1 structure AND, the inverse output of each of the counting triggers is connected to the counting input of the subsequent counting trigger and with the first input 'of the corresponding structure AND of the AND-IPI-NOT element, the second input of which is connected to the corresponding control bus, the input H +1 of the structure AND of the AND-OR-NOT element is connected to the input bus and with the counting input of the first counting trigger, the output of the AND element -OR-NOT connected through the NOT element with installation in entrances 'O' triggers counting of T l and h and w 5 752816 A sh and y with t & l that, in order to increase functional reliability, the output of the element is NOT connected to the third inputs of the first N structures AND element AND-AND LI-NOT. Sources of information taken into account during the examination 1. USSR Copyright Certificate No. 517164, cl. N OZ K 23/26, 1976. 2. Copyright certificate of the USSR ₅ No. 456366, kp. N OZ K 21/36, 1975 (by type). fia. '/