SU748837A1 - Delay device - Google Patents

Description

the driver's master circuit time, the opposite terminals of which are connected to the gate of the field-effect transistor and the cathode of the diode, the anode of which is connected to the inverse output of the H8 flip-flop, the 3rd input of which is connected through a resistor to the power supply line and transistor collector, the base of which is connected to the field drain the transistor and the resistor are connected to a common one of the other power sources and the emitter of the transistor.

The drawing shows a schematic diagram of the delay device.

The delay device consists of an input inverter 1, the output of which is connected with the time of the delay circuit consisting of a resistor 2 and a capacitor 3, and the source of the field-effect transistor 4 with the p-channel, the gate of which is connected to the resistor 2, the capacitor 3 and the cathode of diode 5 The anode of which is connected to the inverse output of RS flip-flop b, the R input of which is connected to the output of inverter 1, and the S input of a resistor 7, another output connected to the supply bus of the device’s power supply, and the collector of the pnp transistor 8, the base of which is connected to the drain of the field transistor 4 p-channel and the resistor 9, the other terminal of which together with the emitter connected to the common bus.

The delay device operates as follows.

In standby mode, the signal at the output of the inverter 1 is zero potential. The capacitor 3 is charged and maintains the locked state of the field-effect transistor 4 with the p-channel positive potential at the gate relative to the source. Trigger b has O at the direct output, and 1 at the inverse. Positive potential of the inverse output through the diode; 5 keeps capacitor 3 in charge. Due to the locked state of field-effect transistor 4, transistor 8, controlled by the base of the drain current, is closed and held in this cocTOHHHia using resistor 9. Positive potential close to the potential of the power source , from the closed transistor 8, supplied to the S input of trigger b, and a zero potential supplied to the R input from inverter 1, fixes the trigger in the etrm state.

When a signal is input to the device at the output of inverter 1, a positive potential appears, due to the fact that the potentials corresponding to the output of inverter 1 and the inverse output of trigger 6 are equal, the diode 5 is locked, and the capacitor 3 starts to discharge to the resistor 2

When the potential at the gate to the cut-off voltage is reduced, the field-effect transistor 4 starts to open and the drain current opens the transistor 8. As at the R input 1 and at the S input O, the trigger b switches and is fixed in this state. Capacitor 3 discharges and maintains the open state of field-effect transistor 4, which feeds the base-emitter junction of transistor 8 to a stable toKOM drain, independent of the voltage supplied from inverter 1. When the input signal is removed, the output of the inverter 1 is 0 that causes the transistor 8 to be locked and the trigger toggle b. The capacitor 3 is charged through diode 5 and closes the field-effect transistor 4 with the p-channel.

invention formula

A delay device containing an RS-flip-flop, the time given by the RC circuit, the transistor, resistors, characterized in that, with the aim of increasing. reliability, noise immunity and expansion of the time delay range, an input inverter, a field-effect transistor with a p-channel, a diode are inserted into the device, and the output of the input inverter is connected to the R-input of the RS-flip-flop, the source of the field-effect transistor, opposite The outputs of which are connected to the gate of the field-effect transistor and the cathode of the diode, the anode of which is connected to the inverse output of the RS trigger, the S input of which is connected via a resistor to the power supply bus and transis ora base of which is connected to the drain of the transistor in the left and through the resistor connected to the common bus power source and the emitter of the transistor. Sources of information taken into account in the examination

1. Author's certificate of the USSR 225904, cl. H 03 K 5/13, 1967.

2. Authors certificate of the USSR 443472, cl. H 03 K 5/13, 1972 (prototype).

Claims (1)

Claim A delay device containing an RS-flip-flop, a timing RC-circuit, a transistor, resistors, characterized in that, in order to increase. To improve reliability, noise immunity and extend the time range of the delay, an inverter, a field-effect transistor with a p-channel, a diode are introduced into the device, the output of the input inverter being connected to the R-input of the RS flip-flop, the source of the field-effect transistor, a resistor and a capacitor of the timing circuit, opposite outputs which are connected to the gate of the field-effect transistor and the cathode of the diode, the anode of which is connected to the inverse output of the RS trigger, the 5-input of which is connected through the resistor to the supply bus of the power source and the collector of the transistor, the base of which is connected to the drain of the field-effect transistor and is connected through a resistor to the common bus of the power source and the emitter of the transistor.