SU748411A1

SU748411A1 - Device for multiplying binary numbers

Info

Publication number: SU748411A1
Application number: SU782618667A
Authority: SU
Inventors: Владимир Львович Волковыский; Александр Иванович Попов
Original assignee: Рязанский Радиотехнический Институт
Priority date: 1978-05-22
Filing date: 1978-05-22
Publication date: 1980-07-15

Description

Изобретение относится к области вычислительной техники и может быть использовано в арифметических устройствах специализированных цифровых вычислительных машин.The invention relates to the field of computer technology and can be used in arithmetic devices of specialized digital computers.

Известны устройства содержащие ре- ⁵гистры множимого и множителя, схему формирования частичных произведений, блок суммирования частичных произведений. Умножение в таких устройствах начинается с младших разрядов множите^ля W ’ И ·Known devices containing PE ⁵ Giustra multiplicand and multiplier circuit forming partial products summation block of partial products. Multiplication in devices starting with LSB multipliers ^A W 'and ·

Недостатком известных устройств является недостаточное быстродействие в связи с затратами времени на приведение двухрядного кода произведения.A disadvantage of the known devices is the lack of performance due to the time spent on casting a two-row product code.

Наиболее близким к изобретению является устройство для умножения двоичных чисел [3] , содержащее сдвигающие регистры множимого и множителя, регист- _Μры поразрядных сумм и поразрядных переносов, блок формирования частичных произведений, блок поразрядного суммирования. Кроме этого в устройстве выход старшего разряда регистра множителя соединен с управляющим входом блока формирования частичных произведений, информационный вход которого соединен с выходом регистра множимого, а выход с одним из входов блока поразрядного суммирования, 'два других входа которого соединены с выходами регистров поразрядных сумм и поразрядных переносов , а выходы — со входами этих регистров.The closest to the invention is a device for multiplication of binary numbers [3], comprising shift registers of the multiplicand and multiplier, regist- _Μ ry bitwise bitwise sums and carries, block the formation of partial products, bitwise summing block. In addition, in the device, the output of the highest bit of the register of the multiplier is connected to the control input of the block for forming partial products, the information input of which is connected to the output of the register of multiplicative ones, and the output with one of the inputs of the block of bitwise summation, the other two inputs of which are connected to the outputs of the register of bitwise and bitwise hyphenation, and outputs - with the inputs of these registers.

Умножение в данном устройстве осуществляется, начиная со старших разрядов множителя.Multiplication in this device is carried out, starting with the highest digits of the multiplier.

Это устройство имеет некоторое преимущество перед вышеупомянутыми устройствами, так как метод умножения со старших разрядов облегчает совмещение устройства умножения с устройством деления и позволяет одновременно с умножением выполнять суммирование.This device has some advantage over the aforementioned devices, since the method of multiplication from the higher digits facilitates the combination of the multiplication device with the division device and allows summation to be performed simultaneously with the multiplication.

Недостатком устройства является недостаточное быстродействие' в связи с затратами времени на приведение двухрядного кода произведения.The disadvantage of this device is the lack of performance due to the time spent on casting a two-row product code.

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Целью изобретения является повышение быстродействия устройства при выполнении многократных умножений.The aim of the invention is to increase the performance of the device when performing multiple multiplications.

Для достижения этой цели в устройство введены дополнительный регистр множителя и преобразователь кодов, причем Выходы старших разрядов регистра множителя и дополнительного регистра множителя соединены со входами преобразователя кодов, выход преобразователя кодов соединен с управляющим входом блока формирования частичных произведений, входы регистра множителя и дополнительного регистре множителя соединены с выходами регистров Поразрядных сумм и поразрядных переносов соответственно.To achieve this goal, an additional register of the multiplier and a code converter are introduced into the device, the outputs of the upper bits of the register of the multiplier and the additional register of the multiplier are connected to the inputs of the code converter, the output of the code converter is connected to the control input of the partial product formation unit, the inputs of the multiplier register and the additional register of the multiplier are connected with outputs of the Bit-by-bit and bit-by-bit transfer registers, respectively.

Схема устройства приведена на чертеже. Устройство содержит сдвигающий вправо регистр множимого 1, блок форми. рования частичных произведений 2, блок 'поразрядного суммирования 3, регистры I поразрядных сумм и поразрядных, переносов 4 и 5, сдвигающие влево регистр множителя 6 и дополнительный регистр множителя 7, преобразователь кодов 8.The device diagram is shown in the drawing. The device contains a shift to the right of the register of the multiplicable 1, block form. partial products 2, block 'bitwise summation 3, registers I bitwise and bitwise, carry 4 and 5, shifting the register of the factor 6 to the left and the additional register of the factor 7, code converter 8.

Работа устройства начинается с исходного состояния. В исходном состоянии в регистре 1 записано множимое, в регистрах 6 и 7 - два компонента (двух- ^грядный код) множителя В регистрах множителя имеется по одному дополнительному старшему разряду. В исходном состоянии в этих разрядах записан ноль.The operation of the device starts from the initial state. In the initial state in the multiplicand register 1 is written in registers 6 and 7 - the two components (two ^d inline code) registers in the multiplier factor has one additional digit up. In the initial state, zero is recorded in these discharges.

В зависимости от комбинации двоичных цифр и старшей паре разрядов регистров 6 и 7, на выходе преобразователя 8 формируются сигналы , С2 , С* , управляющие формированием частичных произведений, равных нулю, прямому коду множимого или его инверсному коду соответственно.Depending on the combination of binary digits and the highest pair of bits of the registers 6 and 7, signals C2, C * are generated at the output of converter 8, which control the formation of partial products equal to zero, the direct code of the multiplicative, or its inverse code, respectively.

Функционирование преобразователя описывается таблицей, в которой приведена зависимость выходных сигналов , от комбинации входных сигналов os^, а_г, и в^ , в 2 , соответствующих старшим парам разрядов регистров 6 и 7.The operation of the converter is described by the table, which shows the dependence of the output signals on the combination of the input signals os ^, and _r , and in ^, in 2, corresponding to the highest pairs of bits of the registers 6 and 7.

. 4. 4

Продолжение таблицыTable continuation

1 1 2. 2. 3 3 и and 5 5 6 6 —* 7 - * 7 О ABOUT 1 1 0 0 О ABOUT 0 0 1 1 0 0 О ABOUT 1 1 о about 1 1 0 0 1 1 .0 .0 О ABOUT 1 1 1 1 ⁰⁰ 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 О ABOUT О ABOUT 1 1 1 1 0 0 0 0 . 1 . 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0, 0 О ABOUT 1 1 θ θ 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 о about 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0

Блок поразрядного суммирования 3, состоящий из группы независимых одноразрядных сумматоров, число которых равно числу разрядов произведения, осуществляет поразрядное сложение частичного произведения с содержимым регистров 4 и 5.The bitwise summing unit 3, consisting of a group of independent single-bit adders, the number of which is equal to the number of digits of the product, performs bitwise addition of the partial product with the contents of registers 4 and 5.

Результат сложения записывается в эти регистры. Одновременно осуществляется сдвиг вправо содержимого регистpa 1 и сдвиг влево содержимого регистров би 7 на один разряд.The result of the addition is written to these registers. At the same time, the contents of register 1 are shifted to the right and the contents of bi 7 registers are shifted to the left by one bit.

Описанная процедура повторяется и раз, где и - число разрадов множителя. В результате, в регистрах 4 и 5 получено в двухрядном коде произведение числа, записанного в регистр 1, на сумму чисел, записанных в исходном состоянии в регистрах 0 и 7. При многократном умножений произведение Из регистров 4 и 5 передается в регистры 6 и 7 соответственно. В следующем цикле умножения оно играет роль множителя,The described procedure is repeated once, where and is the number of bits of the multiplier. As a result, in registers 4 and 5, the product of the number written in register 1 is obtained in two-row code by the sum of the numbers written in the initial state in registers 0 and 7. With multiple multiplications, the product from registers 4 and 5 is transferred to registers 6 and 7, respectively . In the next cycle of multiplication, it plays the role of a multiplier,

В устройстве могут выполняться различные комбинации операций сложения и умножения чисел.The device can perform various combinations of operations of addition and multiplication of numbers.

Например, если в исходном состоянии ' записать в регистры 1,4,5,6,7 числа А, В,С,Д,Е соответственно, то за один цикл умножения будет выполнена операция Ах(Д+Е) +В+С. .For example, if in the initial state 'write the numbers A, B, C, D, E into the registers 1,4,5,6,7, respectively, then in one multiplication cycle the operation Ax (D + E) + B + C will be performed. .

Данное устройство позволяет существенно сократить время выполнения < многократных умножений по сравнению с прототипом.This device can significantly reduce the execution time of <multiple multiplications in comparison with the prototype.

^а1 ^a 1 ^а2 ^a 2 ^в1 ⁱⁿ 1 ^в2 ^at 2 ^С4 ^C 4 ^С2 ^C 2 г 50 g 50 4 4 2 2 5 5 4 4 ¹ 5 ¹ 5 6 6 7 7 0 0 О , ABOUT , 0 0 О ABOUT 1 1 о about О ABOUT о about О ABOUT О ABOUT 1 1 О ABOUT 1 1 0 ⁵⁵ 0 ⁵⁵ 0 0 0 0 1 1 0 0 О ABOUT О ABOUT 1 1 О ABOUT 0 0 1 1 1 1 1 1 О ABOUT 0 0

746411746411

В зависимости от кратности умножения и разрядности сомножителей этот выигрыш составит от 10% до 20% при небольших дополнительных затратах оборудования.Depending on the multiplication factor and the bit depth of the factors, this gain will be from 10% to 20% with little additional equipment costs.

Кроме того, расширяются функциональ- ₅ные возможности устройства по сравнению с аналогами. Предлагаемое устройство позволяет одновременно выполнять различные комбинации операций сложения и умножения чисел. 10In addition, expanding the functional capabilities of the device ₅ nye compared to peers. The proposed device allows you to simultaneously perform various combinations of operations of addition and multiplication of numbers. 10

Claims

The invention relates to the field of computer technology and can be used in arithmetic devices of digital computers. Devices are known that contain multiplier and multiplier registers, a partial product formation scheme, a partial product summation unit. Multiplication in such devices begins with the lower bits of the multiplier 1. 2 . A disadvantage of the known devices is the inadequate performance due to the time spent on bringing the two-row work code. The closest to the invention is a device for multiplying binary numbers 3, containing: its shifting p & multiplier and multiplier gist, bit registers and bit transfer registers, partial product formation unit, bit accumulator unit. In addition, in the device, the output of the higher bit of the register of the multiplier is connected to the control input of the partial product forming unit, whose information input is connected to the output of the multiplicable register, and the output to one of the bit summing block inputs, the other two inputs are connected to the outputs of the bit registers total sums and porass dnrs transfers, and outputs - with the inputs of these. X registers. Multiplication in this device is implified, starting from the higher bits of the multiplier. This device has some advantages over the above-mentioned devices, since the multiplication method from higher-order bits makes it easy to combine the multiplication device with the division device and allows summation at the same time as the multiplication. The disadvantage of the device is the inadequate performance due to the time spent on bringing the two-row work code. 37 The aim of the invention is to improve the speed of the device when performing multiple multiplications. To achieve this goal, an additional mbjitel register and a code converter are entered into devices, with the higher bits of the register multipliers and the additional multiplier register connected to the code converter inputs; the output of the code converter is connected to the control input of the partial product shaping unit; with the outputs of the registers of porous sums and bitwise n © renrosv respectively. Diagram of the device shown in the drawing. The device contains a right-shifting register of multiplicand 1, a block for forming partial products 2, a block of bitwise summing 3, registers (bit sums and bitwise, shifters 4 and 5, the left-shifting register of multiplier 6 and the additional register of multiplier 7, code converter 8, The device starts from the initial state. In the initial state in register 1 is multiplicand, in registers 6 and 7 there are two KosvfflOHeHTa {two-row code) multiplier. In multiplier registers there is about one additional high-order bit. In the initial state, zero is written in these bits. Depending on the combination of binary digits and the upper pair of bits of registers 6 and 7, signals C, Cg, C-t, are generated at the output of compressor 8, controlling the formation of partial products equal to zero, the direct code of the multiplicand or its inverse code, respectively. The operation of the converter is described in the table, in which the output signals of 0.0 Cj are shown as a function of the combination of the input signals С |, а ,, and в, В2, corresponding to the highest pairs of registers 6 and 7. 1 Continuation of the table consisting of a group of independent single-digit adders, the number of which is equal to the number of product bits, performs bitwise addition of the partial product with the contents of registers 4 and 5. The result of the addition is recorded in these registers. At the same time, a shift is carried out in the right content x) register 1 and a shift to the left of the contents of registers 6 and 7 by one bit. The procedure described is repeated n times, where n is the number of multiples of the multiplier. As a result, in registers 4 and 5, in two-digit code, the product of the number written in register 1 is the sum of the numbers recorded in the initial state in registers 0 and 7. For multiple multiplications, the product from registers 4 and 5 is transferred to registers 6 and 7 accordingly. In the next multiplication cycle, it plays the role of a multiplier. Various combinations of the operations of addition and multiplication of numbers can be performed in the device. For example, if in the initial% 1 state we write into the registers 1,4,5,6,7 the numbers A, B, C, D, E, respectively, then in one multiplication cycle the operation Ax (D + E) + B + With. This device can significantly reduce the execution time -i multiple multiplications compared with the prototype. Depending on the multiplicity of volume and size, this advantage will be from 10% to 20% with a small additional cost of equipment. In addition, the functional capabilities of the device are expanded in comparison with analogues. The proposed device allows simultaneous execution of various combinations of operations of addition and multiplication of numbers. Formula invented. A device for multiplying binary numbers, containing shift registers of multiplicand and multiplier, registers of bit sums and bit transfer, block forming partial products block of bit summing, with the output of register multiplicable connected to the input block of partial products, the output of which is connected to one of the inputs of the block of summation, the other two inputs of the block of randomizing are connected to the outputs of the registers of bitwise and serial transfers, and the outputs are connected to the inputs of These registers are characterized by the fact that, with the purpose of increasing the speed of VIA, an additional multiplier register and a code converter are entered into the device, and the outputs of the high-order bits of the multiplier register and the additional multiplier register are connected to the code converter inputs, the output of the code bodies is connected to the control input of the block the formation of partial products, the anodes of the multiplier register and the additional multiplier register are connected to the outputs of the bit-sum and bit-transfer registers of the respective veins about. Sources of information taken into account During the examination 1. Dobronevsky 6. V., et al. Spravchnik on computers, Kiev, Vyusha School, 1976, p. 54-57.

2. Authors certificate of the USSR 357561, cl. (3 06 F 7/39, 1970.

3.Kartsev M. A, Arithmetic of digital ashin. M, Science, 1969, t. 403-408 (prototype).