SU746920A1 - Pulse amplitude-to-digital code converter - Google Patents

Description

The invention relates to the field of computational pulse technology and is intended for the rapid encoding of amplitude-impulse signals and direct current in voltmeters. The time is known to pulse pulse amplitude converters into a digital code containing a linear transmissive and charging device, a storage capacitor, a comparison device, a control device, a generator of discharge current with a key, and a clock pulse generator C and 12. The disadvantage of known converters is that the clock frequency of 100-200 MHz is the limit for them. Also known is a converter containing an accelerated time pulse converter discharging a storage capacitor with two discharge currents significantly different in magnitude 3. The main disadvantage of such a converter is the difficulty of creating two pulse current generators with a high stability of THESE CURRENT relationships, which makes it impossible to achieve a theoretical speed limit. The purpose of the invention is to increase the speed while maintaining the accuracy of the conversion. The goal is achieved by the fact that in a known converter consisting of serially connected input terminals, linear down, charging and comparing devices and a switch, the switch outputs are connected via two pulse switches connected to the code pulse generator with the inputs of the first trigger of the group of junior triggers (n + 1) of the trigger trigger group and, through the first current switch with the charger and current generator outputs, the input terminal is connected to the control terminal via a capacitor is connected between the output of the charging device and the housing, and the output of the comparing device is connected to the switch and the control device, the installation element ypoBHH, the second condensate and the second current switch connected between the switch and the second input of the comparator, the second a capacitor is connected between the second input of the comparator, and the housing; an element of the installed level is connected between the output of the conversion end of the control device And the second input of the comparator, the second current switch is connected to the switch, and the output of the first group of trigger triggers is connected to the subtraction input of the second group of trigger triggers. FIG. 1 shows a functional diagram of the proposed converter; in fig. 2 - time diagrams that show his work. The input terminal of the converter is connected to the control device 2 and through the Line-passing device 3 and the grain device 4 connected in series to the first input of the comparison device 5, the conversion start output of the control device is connected to the unlock input of the switch 7, and the output of the conversion end 8 to the control input level setting element 9 and meter reading inputs 10,11, the inputs of the comparison device 5 are connected via capacitors 12 and 13 respectively to the housing and through the first 14 and second 15 currents The keys to the generator are 16 current. In addition, the second input of the comparison device is connected to the output of the level setting element. The control inputs of the current switches 14 and 15, as well as the control inputs of the first 17 and second 18 pulse switches, are connected to the corresponding outputs of the mutator 7. The pulse inputs of the keys 17 and 18 and the phasing input of the switch 7 are connected to the generator 19 of code pulses, and the output terminals respectively, to the input of the first trigger of the group of lower triggers of counter 10 and to the input (n + 1) of the trigger of the group of higher triggers of counter 11. The outputs from both groups of triggers are connected to the output terminals of the converter 20. The output of the group of Junior triggers is connected to the roar rsivnomu input of a group of senior triggers. The outputs of the comparing device 5 are connected to the input of the transformation control device and the switching input current of the switch 7. Figure 2 shows the diagram of the outputs of the various elements of the transformer Tilyau, V; -: -, -, -: - The converter works as follows The input signal 1 through the open linear transmission device 3 and the charger 4 charges the capacitor 12 to the maximum amplitude of the input signal. Some time after the charge, the control unit locks the linear 1H) descending ycirpolfcTBO 3 And it will switch to commutator 7 to command the start of the conversion. This command is in the phase switch.

Claims (3)

746920 pyefcH with pulses of the generator 19 and turns on the discharge current switch 14 through the capacitor 12. After the first operation of the comparison device 5 and the phasing switch 7 switches on the discharge current switch 15 through the capacitor 13. Since this capacitor has a capacitance 2 times larger, the rate of change tension on it is 2 times less. After the second actuation of the comparator device 5 (in the opposite direction), the discharge is stopped and the conversion ends. During the fast discharge of the capacitor 12, the code pulses through the key 17 are fed to the input (n + 1) of the trigger of the counter 11, and when it is slow through the key 18 to the input of the first trigger 10. Not to distort the result of the conversion. Junior triggers are included in subtraction mode and Shrenos with a group of junior triggers of post-ugyet; to the input subtraction of the older group. Some time after the conversion, the capacitor 13 is reset to the element 9, and from the output of the converter 20 the parallel code is read into the recorder. The maximum speed of the claimed converter reaches when n is equal to the square of the number of quantization levels. The gain in speed is equal to p / 2. Usually, the oscillator clock frequency is 4-5 times reduced at the same time, which makes it possible to use less high-speed phasing schemes and counters and still receive an equivalent frequency frequency above 600 MHz compared to 300-400 MHz in the prototype. Claims of the Inverter Amplitude to Digital Converter consisting of serially connected input terminals, linear-transmissive, charging and comparing devices and a switch, the switch outputs are connected via two pulse switches connected to the code pulse generator with the inputs of the first trigger group of lower triggers and (PI) Trigger group of senior triggers of the meter, and Through the first current switch with a charging device and current generator, the input terminal of the control unit connects A capacitor is connected between the output of the charger and the case, and the connecting device is connected to the switch and the device of deflection, characterized in that, in order to improve the speed while maintaining the accuracy of the conversion, an element is inserted into it the level setting, the second capacitor and the second current switch connected between the switch and the second input of the comparison device; the second capacitor is connected between the second input of the comparator device The chassis, the level setting element is connected between the output of the conversion end of the control unit and the second input and output circuit of the comparing device, the second current switch is connected to the switch, and the output of the first trigger trigger group is connected to the subtraction input group of the second trigger trigger group. Hct04iMKH information taken into account in the examination 1. Converter CT-103, advertising company Jntertechigne, 1973. i. Converter 54168, advertising firm HewJett-Packard 1973. 3. Pazelt, Nucl. Instrum. and Methorfs 1968, 59 No. 2, p. 283 (prototype).