SU726491A1 - Arrangement for testing matrix charge-over switches - Google Patents

Description

(54) DEVICE FOR CHECKING MATRIX SWITCHES

the inputs of which serve as the input of the block, and the output of the lower bit of the shift register is connected to another input of the addition element modulo 2, the output of which serves as the output of the block.

The described device allows to check the correctness of the input and output windings of transformers of matrix switches, built on the principle of summation of currents, voltages or power, and also to check the suitability of the ferrite transformer cores. tori. With Ztom, the number of turns of the flashing windings and the direction of the firmware, performed according to a specific code, are controlled during the verification process.

FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of the polarity determinant.

The device comprises a generator G, a switch 2, a test matrix switch 3, a comparison unit 4, an encoding switch 5 and a polarity detection unit 6.

Block 6 consists of a shift register 7 and an addition element modulo «Z 8.

The generator 1 provides the formation and supply of current pulses using keys to the input windings of the switch 3.

Switch 2, in accordance with the binary code of the address, sequentially selects the corresponding input and output windings of the switch 3. Switch 5 performs a code conversion, in which each value of the simple binary address code is assigned a redundant code corresponding to the firmware of the rows and columns of the switch 3. Comparison unit 4 analyzes the signal in the output winding, comparing its amplitude with a predetermined voltage level, and polarity with the polarity given by block 6, which allows to determine which polarity should be a signal in the selected output winding, according to the specified code for insertion input and output windings.

The device works as follows.

The test matrix switch 3 is connected to the device with the aid of a contacting device.

The test consists in supplying current pulses successively to each input winding of a certain transformer of switch 3 and fixing the presence of an induced signal in the output winding of this transformer with parameters (amplitude, polarity) corresponding to this patching code. The output parameters are monitored visually with an oscilloscope or automatically by the device comparison unit. The change in polarity and amplitude of the signal from the output winding of the transformer relative to the given one indicates, respectively, errors in

the direction of insertion input and output windings or in the number of forgiving turns, the distortion of the waveform allows to determine the material defects of the cores themselves.

In the process of checking the correctness of the switch 3 switch 2 switch 2 you-. One of the output windings of the matrix switch is picked up and connected to Comparison Unit 4, where the polarity and amplitude of the signals in this winding induced as a result of the current pulses of all the input windings bypassed are checked. Then the switch 2 disconnects from the block 4 the checked output winding, selects and connects the following a to the block 4, after which the parameters of the signals entered in this winding are checked in the same way.

A check of the amplitude of the output signals is performed by comparing with a predetermined voltage level. Polarity check

output signals is carried out using block 6.

The principle of operation of block 6 is that the register 7 of the switch 5 enters the firmware code of the input windings of the transformers of the row of the switch 7.

The information from the output of the lower trigger of the register 7 is fed to the input of the element 8, to the second input of which from the switch 5 the firmware code of this output winding of the tested transformer is fed. With

0 each shift cycle, which corresponds to a sequential check of the input windings, the output of element 8 determines the polarity of the signal in this input winding. After checking all the input windings to the second input element 8 of the switch 5, the firmware code of the next output winding is entered, the check of which is carried out similarly to the one described above and so on.

 This potential, which determines the polarity of the signal, comes from the output of block 6 to the output of comparison block 4 and permits the reception of a signal of a corresponding polarity from the output winding of the matrix switch.

In case of a signal mismatch in the output winding of the dissipation potential, coming from block 6, or the amplitude of the output signal differs from the previously specified voltage of the comparison block 4, it generates a fault signal that stops the device with fixing the defect address.

 The main advantage of the invention is the saving of equipment by reducing the number of current switches for driving the input windings of the matrix switch, due to their consistent

J bypass, and also due to the absence of a reference matrix switch and additional nodes for its start. The introduction of a polarity determination unit allows one to automatically control the output signals both in amplitude and polarity using one element of the comparator unit, which simplifies the device for checking matrix 2 x switches.

Claims (3)

1. A device for testing matrix switches, comprising a generator, the output of which is connected to the input of the switch, the first output of which is connected to the input of the coding switch. The second output is with the first input of the comparison unit, and the third output is with the input windings of the matrix switch being tested, the output windings of which are connected to the second input of the comparison unit, characterized in that, to simplify the device, the input polarity detection unit is entered into it which is connected to the output of the coding switch, and the output to the third input block of the comparison. 2. The device according to claim 1, characterized in that the polarity determining unit contains a shift register and an addition element modulo-2 whose inputs serve as the input of the unit, and the low-bit output of the shift register is connected to another input of the addition element modulo 2 whose output serves as a block output. Sources of information taken into account in the examination 1. US Patent No. 3,967,103, cl. 235-153, 1976. 2. USSR Author's Certificate No. 310252, cl. G About F 5/02, 1970. 3. USSR author's certificate No. 209070, cl. G 06 F 15/46, 1966 (prototype).