SU703810A1 - Counter-type adder - Google Patents

Description

 . 1. -, The invention relates to the field of digital computing technology. Accumulating totalizers are known that contain a counting trigger in each bit, an support element, AND and OR l, 2 elements. Closest to this invention is the accumulating adder containing in each bit a counting trigger, the counting input of which is connected to the output of the first OR element, and the output is connected to the transfer output to the subsequent discharge | s. The term numbers must be supplied to the parallel inputs of the bits of the adder sequentially over time, ensuring the time interval between the arrival of two numbers sufficient to form the transfer signal in the bits of the adder, and its transmission through the delay lines connected between every two adjacent bits along directions from the least significant bits to the older ones, which significantly reduces the speed of the adder. In addition, in such an adder, there is no possibility of adding "lfs represented in a sequential code, as well as in the case when one of the addends is represented in a sequential and the other. The aim of the invention is to expand the class of tasks and increase the speed of the adder. This is achieved by offering. The first adder contains an AND element in each section, a RED element, a NAND element, a second and a third OR element, and, besides 1X) GO, a pulse distributor is entered into the adder, its input is connected to the control input of the adder and the outputs are connected to the first inputs of the elements AND-NOT and AND in each type of de, the second inputs of which are connected with. the outputs of the second and third OR elements, and the outputs are connected to the first and second inputs of the first OR element, the third input of which is connected to the transfer output from the previous one

   : 377038

raz da adder; the first bhops of the second and third ORs of each bit of the adder are connected to the parallel input buses of the corresponding bits of the first and second terms, the second j inputs of the second and third OR elements of each bit are combined with the consecutive buses of the first and second terms.

The drawing shows the block diagram About

adder;

Suimator contains counting triggers

1 with counting inputs, elements NAND,

2, elements AND 3, elements OR 4,5, pulse distributor 7, control input 8, parallel input buses of the first and second components 9 and 10, serial input buses of the first and second components 11 and 12.20

The first pulse from the pulse distributor 7 is fed to the inputs of the AND-NOT 2 and AND 3 elements of the first bit, and the first pulse from the pulse distributor 7 is fed to the inputs of the AND-HEY elements 2 and 25 IZ of the 1st bit.

The term numbers presented in the parallel code are simultaneously fed to the paralel buses in 9 and 10 of all the digits of the adder,} 0 after which the start signal is sent to the control input 8. Component bits. through the elements OR 5 and 4 pass through the inputs of the elements AND - H IN 2 and the elements AND

3, the other inputs of which are supplied 35 time-shifted gating pulses of the pulse distributor 7, with the duration of strobe pulses longer, the switching time of the trigger ij

In the case when the value of the discharge of the input element E0–2 corresponds to I, the leading edge of the strobe pulse at the INPUT of the I – NE 2 element is formed by a voltage drop arriving at the counting 5th trigger input 1, and set efo to state 1.

Similarly, the formation of a voltage drop over the current & element IZ, at the same time the differential is formed by the rear edge of the gating pulse.

Thus, at the (1 –1) th digit values of the terms complying with the logical unit, to the counting input. (1-1) th trigger 1 have two trigger signals, the time of which is determined by the duration of the strobe pulse. With e-som (t-1), the counting trigger 1 is consistently taken: 0 ;; ; four

I and O state, as a result, at the output of the (i-1) -th counting trigger, a transfer signal is generated, coming through the element OR 4 to the counting input of the i-fo trigger 1. After a time interval equal to the time interval between pulses of the pulse distributor 7, the formation of the signals of the first 1 tangency trigger 1 at the outputs of the elements AND-HE 2 and AND 3 begins. The process of forming the trigger signals of the T-th trigger 1 is similar to that described.

When summing up the terms represented in the serial code, as well as in the case when one of the terms is represented in the serial and the other in the parallel code, the trigger signal is fed to the input 8 synchronously with the beginning of the first code message of the term represented in the sequential code. The pulse duration of the pulse distributor 7 and the time intervals between them is chosen so that the first pulse of the pulse distributor 7 coincides in time with the first code message of the sequential code of the term, the second with the second code message, etc.

The formation of the trigger signals counting triggers 1 when this happens as described previously.

Sum is read from the outputs of counting triggers 1,

The use in the adder of a pulse distributor, which gates the code signals of the components and simultaneously creates a time interval. Between the arrival of the transfer signal and the recording of the bits of the components in the trigger of the corresponding bits, this adder differs favorably from the prototype, i.e. it is possible to add the numbers presented in both the pargal and in the sequential code without prior conversion. Moreover, in this adder the addends are given ija adder inputs one timeTgao, which allows to increase the speed of the adder.

Claims (3)

Invention Formula Accumulating. an adder containing in each discharge a counting trigger, the counting input of which is connected to the output /: 1 of the first OR element, and the output is connected to the transfer output to the next one, distinguished by the fact that if you increase the speed and expand the class of tasks, the adder contains an AND element in each bit, the NAND element, the second and third OR elements, and, in addition, a pulse distributor, the input of which is connected to the controller of the adder, is entered into the adder, and the outputs are connected to the first inputs of the NAND elements and And in each category, the second entrance which are connected to the outputs of the second and third OR elements, and the outputs are connected to first and second inputs of said first OR gate, the third vhoTs which is connected with the output. the transfer from the previous bit of the adder, the first inputs of the second and third elements OR of each bit of the adder are connected to the parallel input buses of the corresponding bits of the first and second terms, the second inputs of the second and third elements OR of each bit connect the serial and first buses of the first and second terms . Sources of information taken into account in the examination 1. USSR author's certificate number 375645, cl. G 06 F 7/385, 1970. 2. Bukreev, IN and others. Macroelectron circuits of digital devices, Moscow, Sov Radao, 1975, p. 330. 3. Shigin A. G. Digital electronic computers, M., Energie, 1971, p. 215, fig. 9-23 (prototype).