SU684578A1 - Shaft angular position-to-code converter - Google Patents

Description

(54) SHAFT ANGLE CONVERTER - TO CODE

The invention relates to automation and computing, can be used to convert the angle of rotation of the shaft into a code. A known converter of the angular position of the shaft into a digital code that contains an impinging transformer connected to the inputs of adders, the outputs of which are connected to the first inputs of the valves through phase-sensitive rectifiers, the second inputs of which are connected to the output of the pulse generator, and the outputs are connected via a reversible counter and converter " code voltage 1. A disadvantage of this device is its low accuracy. Closest to the proposed shaft rotation angle converter into a code containing a voltage to frequency converter, three sinusoidal signal shapers, a phase synchronous detector, a master oscillator, the output of which is connected to the inputs of two frequency dividers, the output of the first frequency divider is connected to the input of the first descrambler, two the output of which is connected via a sinusoidal shaper to the inputs of a sine-cosine rotating transformer, the output of the control unit is connected to the input of a reversing The first counter, the output of which is connected to the input of the code entry block, the output of the code entry block is connected to the second input of the second frequency divider, the output of which is connected to the input of the second decipher, the output of the first frequency divider is connected to the control input of the code input block 2 |. The disadvantage of the device is low accuracy of converting the angle of rotation of the shaft to the code and low resolving power of the converter, which is explained by the non-linearity of the conversion, the temperature instability of the elements and the difficulty of implementing the converter with a high frequency of the master oscillator. The purpose of the invention is to increase the accuracy and resolution of the converter angle of rotation of the shaft in the code. According to the invention, the goal is achieved by introducing an integrator into the device, the fourth sine wave former, .1,; 1 CHiH; i..i; i, 6: i () K with | 1V11eni, and: onragi .1H1) 1Y wuxi ,: 1IG (.1b, threshold, yiipaiated; and 1He..1b igshr / horses, iipcHJnjja.uHui mc, 1 "code-1p. Non-amplified synchronous legate () | 1 II summator block, non-secondary output lentiy () rat)) a) ei d 5gty pho) world () vata, 11 sine wave.i) H () 1H) voltage is connected to 11e) In () i nholkh summrnrnnmO block, second output of the second den ( and fragora through a quarter (|) ()) mnr () cotton / 1 eniweeo signal with It is connected with the first input of the converter “code - voltage, the second input of which is not connected to the output of the lower digits of the reversible counter, and the output of the converter“ code-voltage is connected to the second input of the single input) unit, which has four inputs)) The remote control terminal is connected to the nerve input of the comparison unit, the second input of the comparison unit is connected to the output of the sine-cosine spin of the transformer, the output of the comparison unit through the selector 1st amplifier is connected to the inputs of the phase and amplitude cHHxpo} iH) ix detector s, the output of the phase detector spphropnogo podk.pochen to the inputs of n | For example, the generator / Kepn to the frequency of a normal b.yuka, whose outputs are nod.pochepy to the inputs b.yuk un) av.1eni, output. P1tudno1CH) syncronyuguyu detector ()) and through nntegrato) connected to the second input | 1 capacitance, 1ite.1 panr w (pn1, third n quadruple 1Q11 1 1khod | | rggo | K) of the radius (rator nod.pochny to the second inputs amnlntudpogo and c) azovnogo nnhron1i 1kh dehekto) OB.

Pa drawing shows a structural electrical diagram of the device. The transducer contains a SNR VNIAC) 1cccc transformer (SQTT) 1, block compared 2, nbirate.chyny amplifier 3, c) azoB1) 1st synchronous detector 4, amplitude synchronous detector 5, voltage converter to frequency 6, threshold unit integrator 8, block 9 of control of reverse iM counter 10 with old and young bits of bits 11 and 12, respectively, shaper 13 of a code input pulse, block of code entry 4, a master oscillator 15, frequency dividers 16 and 17, decoders 18 and

19, the sinusoidal wave conditioners 20–23, the transducer “code-voltage 24, the summing unit 25, the controlled voltage divider 26.

The output of the generator 1 15 is connected to the inputs of the frequency dividers 16 and 17, the output of the divider 16 through the decoder 18 n the sinusoidal signal drivers: 1a

20,21 are connected to the inputs of a sine-cosine rotating transformer 1.

The output of Comparison Unit 2 is through a reversible counter 10, a block for input of code 14 and frequency divider 17 is connected to the input of decoder 19.

B1z1khod of frequency divider 16 through a pulse of input of a code 13 is connected to the control unit, it is input to the input block of the code 14. The first output of the terminal is 19 che () without the driver of sinusoidal voltage 22 is connected to the first input of the summed block 25, the second output of the 1 to 19 final through The driver of the sinusoidal signal 23 is connected to one of the inputs of the converter “code-voltage 24, the second input of which is connected to the output of the younger bits 12 of the reversing counter 10, and the input of the converter“ code-n former 24 is connected to the second input of the sums 11-line unit 25, the output of the latter through the controlled voltage divider 26 is connected to one of the inputs of the comparison unit 2.

The second input of Comparative Unit 2 is connected to the output of the Einus-Coinus (Lo rotates () from transformer 1, and the output of the block is comparable to (P1 2 through the selective amplifier 3 podku 1uchen to the inputs of synchronous detectors 4 and 5. Phase output (; th synchronous detector 4 connected to the inputs of a voltage transformer to a voltage of 6 n threshold block 7, and their outputs are connected to the inputs of control unit 9. The output of an amplitude synchronous detector 5 through an integrator 8 is connected to the second input of a voltage level divider 26. The third Thu Nrty exits the diverter 1 9 are connected to the second inputs of synchronous detectors.

The device works in a general way.

SSCT 1 and reconverts the rotation of the shaft to a voltage, the phase shift of which is proportional to 1N of the angle of rotation: 1a. The voltage from the output winding of the SCRT I is fed to a comparator unit 2, in which it is added in antiphase with a positive signal produced by us. As a result of the addition, the first harmonic of the power supply voltage of the SCPT 1 is extracted and amplified, carrying information about both the phase and amplitude unbalance of the compared voltages. The selective amplifier 3 in the phase difference selection circuit determines the time constant characterizing the dynamic response of the transducer, which to some limits linearly depends on the rate of change of the rotor angle of the SCRT and is eliminated by decoupling the dynamic range of the voltage transducer to frequency 6.

The selected and amplified as a result of the comparison, the first harmonic, equal to the supply frequency, falls on the phase and amplitude synchronous detectors 4 and 5. It should be noted that the on-voltage voltages for the detectors are formulated from the compensating channel, rigidly connected with it, and each other relative to each other, shifted by 90 °. Detector 5 allocates a voltage that is proportional to the magnitude of the following,: 1asovan1 in phase, sign of the value of its width; 1E.1n) t slave mode (p1) 1 ADC, i.e., reduction or subtraction of innulers from the transformer voltages in chaotch (i. Threshold unit 7, in conjunction with the unit. unit 9, generates commands of the operating mode of the reversible counter 10. Amplitude self-current detector 4 1 produces a voltage, pronorona, a very large number of amplitude unbalance of the amplifiers. which through the integrator 8 is fed to the control input of the controlled divide l voltage 26.

The filling of the reversible counter 10 continues until the phase shift between the voltages in the comparison unit becomes 180. As the amount of the unbalance decreases ()) of the imbalance, the frequency of the feedback of the caliper decreases; the equilibrium is eliminated with the help of nopoiOBoro b.yuka 7, the sensitivity threshold of which the coil is equal to H1) in the 1m half of the chain, 1dp1 of the discharge. From the oscillator generator 15, the pulses are sent to frequency dividers 16 and 17 with the same decoupling coefficients. The information from the last three bits of the frequency dividers goes to the numerators 18 and 19, which form portions.

A sinusoidal signal is formed by piecewise linear approximation. The global and amplified voltages from the Einusoidal shaper 20 and 21 are applied to the primary (stator) windings of the ACS 1.

The compensation voltage phase is changed by inputting an initial number into frequency divider 17 (once per period of the generated signal). The number recorded in the upper bits of the reversible counter 10, through the block 14, enters the frequency divider 17 at the moment when in the frequency divider 16 all the triggers go from state "1" and "O. The moment is fixed by the driver, and an input pulse of code 13, which produces a short pulse to write the number to frequency divider 17. The decoder 19 and the sinusoidal signal drivers 22 and 23 operate similarly to nodes 18, 20, 21. The quadratic component is removed from the driver a sinusoidal signal 23, is applied to the converter "code-voltage 24, the amplitude of the signal from which is determined by the number written in the lower bits 12 of the reversing counter 10. At the output, summing up, its block 25 after adding whose phase depends on the number recorded in the reversible counter.

When the number in the lower bits 12 of the counter 10 changes, t small changes in the phase of the compensating voltage occur.

spppmae. with summaries o / and h ;; 2o However, the change in the number in the start-ups would at least be one-to-one jump-wise. The variability of the phase of the KOMiiei; ciii) will be PIA. Ami, 1 ciiiixiiiiH :, detector 5 selects the voltage, npnniipuiiona.ibnoe velpchpepe ampltudnogo 1 / azG) a.1appa, which through the integrator 8 is supplied to the temper.) P1 voltage divider 2 (), KOTo |) imsp e; kompensirukmtsego amplitude voltage ps) etupayup1ego pas one vho.yuv b.kzha 2. Comparative Komnensapn signal, and gtsyuporpionalnogo 1plitudpomu razbalapsu ipformatsponnogo nanr zheny and compensation, the path you v.chenn phase unbalance between said voltages nozvol an increase razrep1ayu1tsuyu the ability and accuracy of the analog-digital converter.

Claims (2)

1. USSR author's certificate No. 222205, O 08 C 9/00, 1964. 2. Authors certificate of USSR M 546922, G 08 C 9/00, 1975.