SU678535A1 - Storage - Google Patents

Description

The invention relates to the field of computer technology and can be used in the construction of devices for storing discrete information. There are memory devices (ZU) containing a magnetically uniaxial film with cylindrical magnetic domains (CMD), on the surface of which there are registers connected to the generators and annihilators of the LMD l (2. One of the known memories contains a magnetornoaxial film with a CMD , on the surface of which the input-output information register is located, connected through the CMD I / O elements to the information storage registers and through the 11MD write-erase elements to the CMD generators and annihilators of the CMD l. signal storage is required for storing the address of discrete registers.The closest technical solution to the invention is a memory that contains (as proposed) a magnetically-disposed film with a CMD, on the surface of which the information input-output register is located CMD with registers of information storage and through the first record-erase element of the MDI with the main generator and annihilator of the CMD and magnetically associated with the main magnetoresistor reading element of the CMD, NMD register connected through the second record-erase element of the CMD with an additional CMD generator and annihilator and magnetically connected with the additional magnetoresistor reading element of the CMD, the first record-erase element of the CMD is connected to the write-erase unit, and the Second is connected to the unit error recording, current source and read amplifier 2. A disadvantage of the known device is its relative complexity. The aim of the invention is to simplify the memory on the CMD.

The goal is achieved by the fact that, in the proposed memory, the main and additional, magnetic resistance readout cells of the LMD are connected to a bridge circuit, in one diagonal of which a current source is included, and in the other - a read amplifier.

FIG. 1 shows the functional diagram of the proposed memory; in fig. 2 - the organization of registers; in fig. 3 entering the CMD into registers, storing information for determining defective places; in fig. 4 - CMD output from information storage registers. On fig. 5 input CMD in the additional register and output from the register I / o; in fig. 6 - entering information into information storage registers; and in fig. 7 - timing charts of the device.

The proposed memory contains a magnetically uniaxial film 1 with a CMD, on the surface of which the information storage registers 2, the information input / output register 3 and the additional register A of the CMD are located. The information storage registers 2 are connected to the information input and output register 3 via the CMD I / O elements 5, which are controlled by the current flowing through the control bus 6. The register 3 is also connected via the first record-erase element of the CMD 7, controlled by the current in the control bus 8, to the promotion channel CMD 9, which connects the main generator 10 and the annihilator 11 NMD. Information I / O register 3 through the passive replicator 12 and the promotion channel of the CMD 13 is magnetically connected with the main magnetoresistor, readout element of the CMD 14 and connected to the passive annihilator 15. The additional register of the CMD 4 through the passive replicator 16 and the advancement channel of the CMD 17 is magnetically connected with the additional The magnetoresistor read element CMD 18 is connected to the annihilator 19, and through the second write-erase element CMD 20 is connected to the advancement channel of the CMD 21 connecting the additional generator 22 and the annihilator 23 CMD. The recording element of the CMD 20 is controlled by the current on the control bus 24.

The main 14 and the additional 18 magnetoresistor elements of the CMD reading are connected to the bridge circuit and connected via busbars 25 and 26 to one pole of the current source 27, switched on jioMy into one dialer bridge circuit.

The other pole of the current source 27 is connected to resistors 28 and 29, which are connected respectively to the DZ and 31 buses to elements 14 and 18, and to conductors 32 and 33 to the inputs of a read amplifier 34 included in another diagonal of the bridge circuit. The output of the memory amplifier is connected to the error fixing unit 35 and to the read driver 36. A read generator 36 is connected to an output register 37, which is controlled from an error fixing unit 35 and a control unit 38. Block

38 control also connected to the unit

39 controlling the magnetic field, to which the cat-switches 4O and 41, constituting the rotating magnetic field, are connected, to the I / O control unit 42,

To which the transfer control bus 6 is connected, to the information recording-erasure control unit 43, to which the control bus 8 of the write-erase element of the CMD 7 is connected, to the error recording unit 44, to which the control-erase-write bus 24 is connected CMD 20. Block 44 is also controlled from block 35 ,,. Block 43 is connected to input information register 45 and block 35, block 42 contains address register 46, and block 38 contains command register 47.

The connection point 48 of the magnetoresistor reading elements of the CMD 14 and 18 is derived with the help of the bus 26. on the contact pad 49 (Fig. 2). The other ends of elements 14 and 18 are derived by tires 30 and 31 to contact pads 5О and, 51. The direction of motion of the CMD in the registers and channels of advancement of the CMD is indicated by a thin arrow D. The motion of the CMD is caused by known methods, for example, by resetting the magnetic film applications with a rotating magnetic field H created by the coils 40 and 41 (the direction of rotation is conventionally shown in the figures by the circular vector H) The number of bits (periods) in register 3 I / O is equal to the number of bits (periods) register 4, the number of bits from replicator 12 to read element 14 to write-erase element 7 is equal to the number of bits from replicator 16 to read element 18 and to write-erase element 20 (positions occupied by A circle 52 shown schematically, a defective place - 53).

Claims (2)

The proposed device operates as follows. To decapitate defective information stored registers (loss of defects, i.e., open information registers), at least one is entered, and a parameter of two, MD 54 in each formation storage register 2 (Fig. 3). Then, the CMD 54 is advanced at least once through all the positions 55 of the information storage registers 2 and output by the input / output elements 5 to the register 3 (Fig. 4). At position 55, corresponding to the information storage register 2, with a defect 53, there is no CMD 54. 3 I / O advancing through the register, the CMD 54 passes a passive replicator 12, each divided into two domains, one of which continues to advance through the I / O register 3 towards the write-erase element 7, and the other through channel 13, where it is registered by read element 14 and then co-lapses on the annihilator 15. The bob-shaped passage through element 14 of the CMD 54 causes imbalance of the bridge, on different shoulders of which are included elements 14 and 18, resistors 29 and 2 $; The current source 27 is turned on to one diagonal of the paddle, and the other is balanced reading amplifier 34. The imbalance of the bridge produces an input signal, such as a positive one, which is amplified by amplifier 34 (in Fig. 7a, graph D, the CMD passes through element 14, the graph is the read signal on the amplifier read) When CMDs corresponding to a defective loop must pass, the absence of these CMDs (position 55, Fig. 5 does not cause unbalance of the bridge and there is no signal at the input of the amplifier. The absence of a signal on the read amplifier at the moment of passing the CMD when determining a defective loop causes fixation unit 35 to trigger omti6oK, and the write signal to the additional register (in Fig. 7a, graph D) is generated, exciting the control bus 24 of the write-erase 2O control element, which transmits the CMD from the generator 22 to the register 4 (Fig. 5). At the same time, all the CMDs output from x reg A bus 3 input and output bus of control 8. In this case, the CMD is transferred by the write-erase element 7 to the channel 9 and follow to the passive annihilator 11, where it collapses. Thus, in the register positions 4 corresponding registers 2 store information with a defect 53 , CMDs are present, but in the positions corresponding to suitable registers they are not. CMD in the additional register is passed in the same way as in the I / O register, pass through the assisted replicator 16, channel 17, read element 18 to the passive annihilator 19, element 18 p oiskhodit ruguyu unbalance of the bridge in direction, and is a negative input signal (FIG. 7.6 Oosh schedule -nf domains in the additional register). When the memory is used in the modes of recording or reading information at times, for example, writing (Fig. 6) information 1,0,1,1, O, 1 ..., which can get into the defective loop, CMD J passes through element 18, which causes a negative signal at the output of the amplifier 34, blocking the recording signal is canceled in block 35, and the input crossing detection signal U p is removed (dz (fng. 7.6). Thus, the next bit from the register of input 45 is delayed at this moment arrival position (time), where the CMD in the additional register is missing, i.e. T is the moment of writing in the data storage register 2 without a defect (Fig. 6). In the I / O register 3 at this moment information is not recorded (position 55 and 52 in Fig. b). The information is read in a similar way. On a negative signal (Fig. 7.6) permission to enter information into output register 37 is removed, and the position corresponding to register 2 with defect 53 is skipped during output. Control unit 38 sets the device operation mode (write, erase, store, output, determine defective loops, etc.) e.) depending on the state of the register 47 and A team synchronizes the operation control unit 39 the magnetic fields with the other device blocks (FIG. 7a and 7b synchronization schedule). The information address is set by the I / O control unit 42 regardless of the presence of defective registers according to the state of the address register 46, and the I / O time is synchronized by the control unit. For the case where the defect 53 is of such a nature that it continuously generates the CMD, the defective register is determined as follows. Information is stored in the information storage registers containing only O, i.e., CMD are entered. Then this project goes at least once along the entire length of each registrar of information 1m. E. The speed of the rotating magnetic field vector must be no less than the number of information bits jie) and by driving the bus 6 through the I / O elements 5, the contents of the information registers 2 are output to the I / O register 3. This information is promoted through the I / O 3-register, passes through the passive replicator 12, the read element 14, and the write-delete element. During the passage of information corresponding to the information register, in which the defect continuously generates the CMD through element 14, there is a CMD that causes imbalance of the bridge and a positive signal at the input and output of the read amplifier. This moment is recorded and the CMD is entered into an additional repl. Page, and from the I / O register 3, the CMD is derived. When writing information in this case, determining the point in time for writing to the defective register of information occurs in the same way as described earlier and also causes a delay in recording the next bit from register 45. Using the proposed device allows you to simplify work algorithms, reduce hardware in order to detect defects and in the process, the slave will perform diagnostics of information registers and reorganize the operation of the device without the involvement of other hardware. At the same time, the number of read ropes is reduced. Since the same read amplifier is used to read information from the storage registers and to read information on the presence of defects. Claims a storage device containing a magnetically uniaxial film with cylindrical magnetic domains on the surface of which an information input-output register is located, connected through input and output elements of cylindrical magnetic domains C with information storage registers and through a first write-erase element of cylindrical magnetic domains - with a main generator and annihilator cylindrical magnetic domains and magnetically bonded with slender magnesium: - resistor element of cylindrical reading additional domains, an additional register of cylindrical magnet domains, connected via a second recording element — erasing cylindrical magnetic domains with an additional generator and annihilator of cylindrical map domains and magnetically coupled with an additional magnetic resistor reading element of cylindrical magnetic domains, the first recording element erasing cylindrical magnetic domains with the write control-erase information control unit, and the second with the error recording block, current source and device divisor read, otlichayu.schees in that, in order to simplify the device, the primary and secondary read elements magnitoreeistornye cylindrical magnetic domains are connected into a bridge circuit, in one diagonal of which is included a current source, and the other - the read amplifier. Sources of information taken into account in the examination 1.RGOS. IEBE, V. 63, No. 8, 1975, p. 1176. 2. US patent No. 379245O, CL. 34O-174 12. 02.74. in Sj 9 / O-o-o-o-o-t-f oh-oh-oh- fS0 0 0 fPut. 0 0 ui.5 P 0 IPU2 6