SU660280A2 - Device for adaptive correcting of signal - Google Patents

Description

The device works as follows.

The next sample of the signal, arriving with the period T from the communication channel, contains ten binary bits. Each bit of the ten-sample signal is entered into input register 1, having previously shifted its contents one row to the right. At the same time, the content of the rightmost edge is erased.

In multiplier 2, all the signal samples stored in input register 1 are multiplied alternately by the corresponding gain factors accumulated in register 17. The results of these multiplications are summed in accumulator 3, the output of which, at the end of the cycle of multiplications and summations corresponding to the current period T, is removed. signal to the consumer.

Further, in the detector 20, the analysis of the corrected signal value determines the current value of the absolute value of the error, which is entered into the lower bits of the register 19. At the same time, the absolute value of the current error in block 18 determines its sign, which is fed to the input of the register 6, the contents of which shifts one bit to the left.

During each multiplication of a signal sample from input register 1 by the corresponding coefficient value from register 17, during the cycle defined by period 7, this factor is corrected, for which block 4 determines the sign of the alternating signal sample received at the input of register 5 , the content of which is shifted by one bit. This is followed by a refinement of the zinlenie coefficients of the offset corrector. For this, the current value of the first coefficient from register 17 is entered into the correction adder 16. Then, when the control signal at the input of the matching element arrives, the sign of the increments of the coefficient is written to the sign bit of the register 19, the high-order bits of which are corrected adder 16. The relative position of the content of the corrective adder 16 n summable increment value in the register 19 is selected so as to ensure the necessary weighting of the absolute value of the error . The increment thus obtained is signed with the contents of the correction adder 16.

Until the control signal appears at the input of the match element 12, the contents

the register 19 is cyclically shifted so that against the corresponding inputs of the corrective adder 16 there is another absolute error value, obtained on the subsequent operation cycle of the device but with respect to its previous value. By calculating the next sign, the resulting increment is added to the content of the correction adder 16. Thus, the refinement of the coefficient continues until the correction factor of this coefficient is completely finished, the value of which is then written off to register 17.

The refinement of the next tap gain factor begins with the fact that the contents of input register 1 are cyclically shifted one bit to the right and in block 4 the sign of the next current is determined.

signal samples, and the contents of register 5 is shifted by one bit. At the same time, the next value of the coefficient from register 17 is entered into the correction adder 16. Next, the procedure for correcting the gain of the retraction is repeated.

After refining the last tap gain factor, the contents of register 19 are additionally shifted so that, against the outputs of the detector 20, there is

the early value of the absolute error, which in the next cycle of operation is replaced by the new current error value from the output of the detector 20.

Claims (1)

Invention Formula Adaptive signal correction device for aut. St. No. 499681, characterized in that, in order to reduce the correction time, a gain increment register has been entered into it, a signal detector Error, assembly element and four matching elements, the output of each of the correlators being connected through the corresponding matching element to another input each of which is given a control signal to the input of an assembly element whose output is connected to the input of the "Sign Digit of the gain increment register", the output of the "Sign Bit of which is connected to the input of the corrective sum tori, the outputs of the higher bits of the gain increment register, one of which is connected to one from the inputs of the lower bits of the gain increment register, each of which is connected to the corresponding output of the signal detector "Error, are connected to a correction adder, and the entrance is the next one connected to the output of the storage device.