SU660244A1 - Analogue-digital converter - Google Patents

Description

and the third input is connected to the output of the clock generator.

The structural electrical circuit of a ycrpoii is shown in the drawing.

The analog-to-digital converter contains a comparator 1 device, a 2 code converter — voltage, reference voltage sources 3, a sweep counter 4, element 5, a clock pulse generator b, an output code counter 7, an automatic limit switch 8, an analyzer 9, a quadrator 10 , a period former 11 is transformed, a controlled divider 12 and a zero determiner 13.

An analog-to-digital converter works in the following way.

Since the beginning of the conversion, the clock pulses from the generator of 6 clock pulses through the controlled divider 12, the division factor of which at the initial time is equal to "1, go to sweep counter 4. Minor bits of sweep counter 4 are connected to the leading weight resistors of the R-2R matrix 2 code voltage. Such a connection ensures the formation of a reference voltage i / oT with a uniform arrangement of values. The transformed voltage U (t) through the normalizer of the automatic limit switch 8, switched on with the division factor Kg 8, is fed to the input of the comparison device 1. To the second input of the comparison device 1 from the converter 2, the code - voltage is applied to the reference voltage. By comparing the values of the converted voltages U (t) with the values of the stepped reference voltage Uou, the comparator 1 selects those f / on values for each clock cycle. which exceed the value of L / (t}. The pulse sequence from the output of the comparison device 1 is fed to the analyzer 9. The analyzer 9 provides processing of the output signals of the comparison device 1 and the selection of pulses at those moments of the clock sequence when and (t) Lon. In addition, the output analyzer 9 pulses are distributed across channels

-N + - for a U (t) value above the t axis;

-N- - for U (t) values below the i axis;

- | yV | - (module pulses) - modulated L + and L- pulses.

From the output of the analyzer 9, depending on the conversion mode, the pulses through the respective channels are fed to the input of the counter 7 of the output code. When converting a DC voltage with an interference imposed on it (average value conversion), L + pulses are received at the input of the output code counter 7 with positive voltage and N pulses with negative voltage. In the case when the level of periodic interference exceeds the average value of the constant voltage.

the input of the output code counter 7, operating in the reverse mode, receives pulses N + and. Depending on the quantitative ratio of the pulses N + and jV- - the polarity determiner 13 provides information about the polarity sign of the converted DC voltage in the binary code. When converting the average value of the alternating voltage, the output of the counter of the output code 7, operating in the summation mode, impulses the pulses of the module N. When converting the effective value of the alternating voltage, the pulses of the modulus

the input of the counter 7 is passed by means of signals generated by the quadrant 10. From the output of the counter 7, information in the form of a binary parallel code is removed on command from an external equalizer. The value of the code determines the value of the integral for the integration interval T, The value of the integral of integration VT in the form of a binary parallel code is taken from the output of sweep counter 4.

Claims (2)

Invention Formula An analog-to-digital converter that contains two sources of reference nanotechnology, the outputs of which are connected by the converter inputs code — a nanometer, the control input of which is connected to the control output of the sweep the counter, and the output is connected to the first input of the comparator, a clock pulse generator, an output code counter, the input of which is connected to the output of the AND element, characterized in that, in order to extend the functionality of the device, an analyzer, a conversion period former, quadrator are added to it , polarity determinant, controlled divider and automatic limit switch, the output of the automatic limit switch is connected to the second input of the comparator, and the input to the quad input and the first output of the analyzer, the second output of which is connected to the inputs of the conversion period generator, the polarity determinant and the first input of the And element, the second input which is connected to the output of the quad, the first input of the analyzer is connected to the output of the comparator, and the second input is connected to the first output of the controlled divider, the second output of which the scanning of the connections to the input of the counter, the second output of the scanning counter is connected to a first input of controllable divider, a second input coupled to the output of the conversion period, and a third input coupled to an output generator clock pulses. Sources of information taken into account in the examination 1. USSR author's certificate No. 333697, cl. H 03 K 13/20, C 06 3 / 00.1970. 2. USSR author's certificate number 349101, cl. H 03 K 13-20, 1970. t)