SU651494A1

SU651494A1 - Arrangement for cyclic phasing of binary signal transmission apparatus

Info

Publication number: SU651494A1
Application number: SU772531642A
Authority: SU
Inventors: Сема Павлович Вольфбейн; Мария Алексеевна Луговская; Валерий Николаевич Сараев
Original assignee: Предприятие П/Я А-1221
Priority date: 1977-10-14
Filing date: 1977-10-14
Publication date: 1979-03-05

Description

Изобретение относитс к св зи и может использоватьс в передающей и приемной част х систем передачи двоичных сигналов.This invention relates to communications and can be used in the transmitting and receiving parts of binary signal transmission systems.

Известно устройство циклового фазировани аппаратуры передачи двоичных сигналов , содержащее регистр сдвига и последовательно соединенные дешифратор, счетчик и решающий блок, а также блок стробировани I.A device for cyclic phasing of a binary signal transmission equipment is known, which contains a shift register and a serially connected decoder, a counter and a decisive unit, as well as a gating unit I.

Однако известное устройство л-овольно сложно.However, the known device is l-difficult.

Целью изобретени вл етс упрощение устройства путем исключени п-дещифраторов и п-счетчиков.The aim of the invention is to simplify the device by eliminating p-decipherors and p-counters.

Дл этого в устройство циклового фазировани аппаратуры передачи двоичных сигналов , содержащее регистр сдвига и последовательно сюединеиные дешифратор, счетчик и решающий блок, а также блок стробировани , введен блок коррекции, вход которого соединен с выходом блока стробироваии , а выход подключен к входу дещифратора , другие выходы которого подключены к разр дным входам регистра сдвига, разр дные выходы которого по тключены кTo do this, a correction unit whose input is connected to the output of the gating unit, and the output connected to the input of the descrambler, other outputs are entered into the cyclic phasing device of the binary signal transmission equipment containing the shift register and sequentially which are connected to the bit inputs of the shift register, the bit outputs of which are connected to

другим входам дешифратора и блока коррекции .other inputs of the decoder and the correction unit.

На чертеже приведена электрическа схема предложенного устройства.The drawing shows the electrical circuit of the proposed device.

Устройство циклового фазировани аппаратуры передачи двоичных сигналов содержит блок 1 стробировани , регистр 2 сдвига , дешифратор 3, счетчик 4, решаюший блок 5 и блок 6 коррекции. Регистр сдвига состоит из чеек 7.The device for cyclic phasing of the binary signal transmission equipment includes a gating unit 1, a shift register 2, a decoder 3, a counter 4, a solving unit 5 and a correction unit 6. The shift register consists of cells 7.

Устройство работает следующим образом .The device works as follows.

В каждом цикле принимаемого сигнала содержитс N бит, из которых Е бит нринадлежит синхрокомбинации. Рассто ние между любыми двум соседними битами сии5 хрокомбинации равно г бит. Номера чеек 7 регистра сдвига, подключенных к выходам дешифратора 3, определ ютс следующим соотношением: i к-г + 1, где к - целое число, лежашее в интервале 1 к logt,.Each cycle of the received signal contains N bits, of which the E bit belongs to the sync pattern. The distance between any two adjacent bits of this syrup 5 crystal combination is equal to g bits. The numbers of the shift register cells 7 connected to the outputs of the decoder 3 are defined by the following relationship: ikg + 1, where k is an integer lying in the range of 1 to logt ,.

Принимаема в каждый такт двоична Accepted in each beat is binary

Claims

0 information is fed to the input of correction block 6 and, if the bit outputs (i -.) Cells 7 of register 2 are currently written in the parallel binary code, the number M is compared with the (M + 1) -th bit of the sync combination. When they coincide, the outputs of the decoder 3 connected to the bit inputs of shift register 2 appear, the number (M + 1), which is recorded in the first and i-e cells 7 of shift register 2 with the next clock cycle. Moving forward in the last 2, the binary number (M + 1) appears on the bit outputs (i - 1) of the cells 7 through the g ticks and is used when comparing the next bit of information with the (M + 2) sync combination bit. In each successive clock cycle at the outputs of the decoder 3, connected to the bit inputs of shift register 2, a Methe double number was set, which is determined by the information bit received at the moment, and the bit received at the r clock earlier, and in no way associated with the value of the information bits received in the interval (from the first preceding to (d - 1) -th, inclusive). Due to the fact that the binary numbers coming from the outputs of the decoder 3 connected to the bit inputs of the shift register are stored in it separately, the input information in the device is divided into r streams so that the input signal bits located in each of the streams from each other at g clocks. Information processing within each of the threads is carried out independently of other threads. The M number, which is written from the outputs of the decoder 3 to the shift register, is each time equal to the number of bits that coincided with the start of the sync pattern in that stream, the bit of which entered this clock at the input of the gating unit 1. If the next clock compares the last bit bit sync and while they are recorded coincidence, with the output of the decoder 3 squeals the signal to counter 4, marking the detection of sync pattern in this bit stream. When such a signal is repeated several times. For a given flow from the output of counter 4, a signal arrives at decision block 5, and the latter adjusts the receiving part of the equipment. If, at the moment when the binary number M was written in the first 7 cells, the received bit did not coincide with the (M + 1) -th sync bit, the correction unit 6 generates a control signal to the input of the decoder 3, which At the outputs of the decoder 3, connected to the bit inputs of the shift register 2, a number appears that reflects the maximum number of the last bits received in a given stream that coincided with the start of the sync pattern. Thus, the correction unit 6 eliminates the possibility of skipping the sync pattern in the cycle of the received signal. The proposed device allows quick synchronization with a small amount of memory. Claim device A cyclic phasing apparatus for transmitting binary signals containing a shift register and a serially connected decoder, counter and decider, as well as a gating unit, in order to simplify the device by eliminating p-decoders and p-counters, a correction block is introduced whose input is connected to the output of the gating unit, and its input is connected to the input of the decoder, the other outputs of which are connected to the bit inputs of the shift register, the bit outputs of which are connected via eHbi to other inputs of the decoder and correction unit. Sources of information taken into account in the examination 1. Patent of Germany No. 2118018, cl. 21 a 136/24, 1976.