SU648973A1 - Device for interfacing communication channel with peripheral sources and peripheral receivers - Google Patents

Description

TOBs but can not provide m. Call. Therefore, this device can only be used to collect information, but cannot carry it out to objects, in the known device there is no possibility of leveling, prioritizing. (The system of priorities is adopted in it (in the order of increasing addresses unacceptable for many characteristic modes of operation, for example, if information is evenly distributed in unfavorable conditions, objects with small address numbers appear; reaction time (time interval between the appearance of the object information and the beginning of the transfer, the address of the object) in a known device is comparable with the time of the transfer of the address sequence. This entails a decrease in the system capacity as a whole. The device is an increase in bandwidth. For this purpose, in the proposed device, each addressing unit further comprises a command decoder, second and third input elements, and the second and third control are triggers, the second and third address elements are the second and third output elements, and the fourth matching element the element And readiness, the second, third, fourth and fifth elements of the OR, and the outputs of the first second and third matching elements are connected with the first, second, and third stages If the first, second, and third outputs of the command injector are connected to the first & input inputs of the same name AND, the second inputs of the first and second input elements AND of each address block are connected to the output of the same peripheral source, the output of each peripheral receiver is connected to the second input of the third input element AND the same addressing block, the outputs of the second and third analogue M8NTOV AND -consistency, respectively, with the vnizhnazh inputs of the same name control kakih triggers, single the stroke of each control trigger is connected to the first input of the address element of the same name AND the first input of the same output element AND, the single input of the second element SH, the output of which go to the second input of the control element I, to the input of the initial setup the address bits of the address and the first input of the element And readiness; the second exit of which is connected to the output of the first discharge of the counter of the address bits; The address elements I are connected to the forward output of the address code generator, the return output of the address code generator is connected to the second input of the second address element AND, the outputs of the first and second address elements AND are connected, respectively, to the second and third inputs of the third OR element, whose output connected to the input of the fourth matching element and the first move of the fourth element OR, the second input is connected to the output of the third address element AND, the output of the fourth matching element is connected to the information the ion input of the communication channel, the output of the fourth element OR is connected to the second end of the inequality element, the output of the old bit of the address digit counter is connected to the second inputs of the three output elements AND, and to the second input of the first element OR whose output is connected to the zero inputs of all control triggers of the first and second output elements And are connected, respectively, with the first and second inputs of the fifth OR element, the output of which in each addressing unit is connected to the input of the same peripheral port regular enrollment, the output of the third AND gate output is connected to the eponymous ahodom peripheral receiver. Figure 1 shows the electrical structure of the device; in fig. 2 Functional scheme of the device addressing block. The device contains a communication channel 1, addressing blocks 2, the first control output 3 of the communication channel, the second control output 4 of the communication channel, the information output 5 of the communication channel, the information output 6 of the communication channel, peripheral sources 7, peripheral receivers 8 The addressing block 2 contains-; matching elements 9-12, a command decoder 13, input elements AND 14, 15, and 16, control triggers 17, 18, and 19,

And 20, 21, and 22 apresnye units, And 23, 24, and 25 output outputs, OR 26-ZO elements, And 31 control element, 32 address bits, 32 address codes, Shifter 33, address inequality element, 35 .

The addressing unit 2 provides the following functions: it transfers the code of the address of the object of the peripheral source if it contains information ready for transmission; perceives the address code when calling the object of the peripheral receiver from the communication channel.

The dialing of the peripheral device, ready to transfer information, is carried out as follows. An Election with Direct (Inverse Address) command is transmitted from the communication channel to outputs 3-5. If none of the peripheral sources 7 has information ready for transmission, then this combination is repeated.

When a Ready signal appears at the output of a peripheral source at the output

4 channels of communication receives a series of synchronization signals, which provide a survey of the bits of the drivers 33 of the address code of all objects that have information ready at the moment to be transmitted. When polling shaper 33 code, the address of the object is transmitted from the output

5 channels of communication. In addition to the transfer of information, the communication channel is involved in the allocation of the priority object. This is done by comparing each bit of the address of the object with the information currently being transmitted to output 5 of the communication channel. If a unit signal is transmitted over a communication channel, and zero is contained in the address address address being scanned, then this object is & crashes the transfer address. For example, objects with addresses 7 (0111) and 5 (OiOl) are ready for transmission. When polling the older two bits, both objects transmit the address. When polling the third

, an object with the address 5 offs1 with the address, since its address contains zero, and the communication channel received (from device number seven) one.

Channel Interface Device

The communication with peripheral sources and peripheral receivers can operate with direct and inverse addresses of objects. When using direct addresses, the highest priority is given to

object with a higher address number, and when using inverse addresses with a lower one. For example, if objects with addresses 1 (OOO1), 5 (OrUl) and 7 (0111 /) are ready for transmission, then for direct addressing the order of selecting objects will be 7, 5, 1, and for inverse addressing - 1 :, 5 , 7 (the inverse address codes of these objects are, respectively, then 101О, YuOO).

0

If there is information ready for transmission (upon receipt of the signal from the output of one of the peripheral sources) the Dial command with the direct address

5 opens the input element AND 14, sets trigger 17 to the state, prepares elements 20 and 23. At the same time, through the OR 26 element, the counter is reset.

About 32 and the control element I 31 opens, through which the synchronizing signals from the output 4 of the communication channel arrive at the counting input of the counter 32. The signal from the first discharge of the counter 32 (along

5 to the first clock pulse) opens AND 35, which transmits the Ready signal to input 6 of the communication channel (via the OR circuit 27). Subsequent synchronizing pulses, acting on the counter 32, interrogate the bits of the shaper 33 of the address code. From the direct output of the driver of the address code 33, the direct address code is through the address element I 20 and the element. OR

5 27 is fed to the input 6 of the channel and through the OR element 28 to the input of the inequality element 34, to the second input of which a signal is fed to the communication channel. In this case, the communication channel

0 performs the assembly function for all objects. If zero is recorded in the format 33 code generator and the unit signal is written on the communication channel, the inequality element 34 generates a signal that (through the OR circuit 29) triggers trigger 17. Thus, the counter 32 is transferred to the zero state and The object stops sending the address until the end of the current loop.

0 links If this object transmits the address alone or has the highest priority, then the counter 32 terminates its operation and the signal from the output of its last bit through the output element 23 and the OR element 30 enters the input of the peripheral source, thereby permitting the transfer of information. At the same time through the element OR

29, a zero setting signal is applied to trigger 17.

When a manda arrives from the ctml. Dialing with a tsherny alres, emend 15 opens, the trigger 18 becomes one, and elements 21 and 24 are ready for operation. From this moment on, the device works as described. The difference is that from the driver 33 of the address code to the input b of the communication channel and to the inequality element, the inverse address code is returned.

Presence of regimes of electing from pr. By using the inverse and inverse address codes, you can set priorities in order of increasing and killing addresses of objects, as well as align the priorities of the device.

The alignment of the prioritized objects is accomplished by interleaving the sniffing sequences with the direct and inverse addressing systems. At the same time, the communication channel alternates between the commands Dialing and Direct. address and Election with inverse address. With the same number of synchronization sequences with direct and inverse addressing, the conditions for ifff of all objects become; Og-Shakov, i.e. they all have the same (in a statistical sense) priority level. Varyu this ratio, you can adjust the conditions for the election of objects.

An object call (for outputting information to the communication channel and peripheral receiver 8) is carried out by sprinkling its address on the output 5 of the communication channel. Preliminary communication channel 1 sends the outputs S 5 to the command switch. Those who are ready to receive information (the signal from the peripheral receiver output), on the command from the element 16 is hidden, the trigger 19 is transferred to the single position, the elements 22 and 25 are connected to the oTicpbi ™.

, with in the initial state it is -32 „.

The address code of the object is transmitted via the output 5 of the communication channel and accompanying the output by 4 synchronization signals, which, through the epheme 31 axis, “live with the counting 32. At the same time, the address code from the direct, output of the forwarder is 33 address code posts through element 22 and element RSH 28 to the input of element 34 is unequal,. compares it with the code, by calling No. # over the communication channel.

The mismatch of any bit of an address address element 34 of inequality (by quenching the trigger 16 and counting at 32) turns off the addressing device.

If the address codes match, then through the key 25 a signal is sent to the input of the peripheral receiver, preparing it for receiving information.

Thus, the proposed device ensures the performance of all functions.

required for interfacing the communication channel with peripheral information receivers and peripheral information sources. It selects the peripheral sources ready for transmission and calls them at. At the same time, flexible control of the priority system is ensured and a sufficiently short response time, which does not exceed two working cycles.

The economic effect of the proposed device is to increase the coefficient of use of the equipment (due to the provision of information output mode) and to increase system capacity, and consequently, the number of connected objects (due to a more flexible priority system and response time).

Claims (2)

Invention Formula . A device for interfacing a communication channel with peripheral sources and peripheral receivers, containing P - blocks. Addresses, each of which contains the first, second, third coherent elements, an unequal element, an address digit counter, address code formaker, AND control element, AND first input element, first control trigger, AND output, first OR element and the inputs of the first three matching elements are connected, respectively, to the first control, second control and information output and communication channel output of the third matching element is connected to the first input nonequivalence element whose output is connected to a first input of the first element. OR, the outputs of the address bits counter are connected to the inputs of the address code generator, the count input of the address bits counter is connected to the output the control element I, the first input of which is connected to the output of the second matching element, the output of the first input element I is connected to the single input of the first control trigger, characterized in that, in order to increase the throughput of the device, each addressing unit further comprises a command decoder, the second and the third input elements And, the second and third control triggers, the first, second and third address elements And, the second and third output elements And, the fourth matching element, the element And readiness and, the second, third, fourth and fifth elements OR, and the outputs of the first, second and third matching elements are connected, respectively, with the first, second, third inputs of the instruction decoder, the first, second and third outputs of which are connected, respectively, to the first inputs of the input elements of the same name And, the second inputs of the first and second input elements And each addressing block are connected to the output of the same peripheral source, the output of each peripheral receiver is connected to the second input of the third input element And the addressing block of the same name, the outputs of the second and third input elements AND are connected, respectively, to the single inputs of the same control trigger, the single output of each control trigger is connected to the first input of the same name address element And, the first input of the same output element And by the same input of the second OR element, the output of which is connected to the second I of the control element AND, to the input of the initial setup. counter address bits and the first input element And readiness, the second The input of which is connected to the output of the first digit of the address address bits, the output of the element And readiness is connected to the first Bxouoiv), with this element VIJ, the second inputs of the first and third address elements And are connected to the direct output of the address code generator, the return form output - the address code code is connected to the second input of the second address element AND, the outputs of the first and second address elements AND are connected, respectively, to the second and third inputs of the third element OR. the output of which is connected to the input of the even coordinating element and the first input of the fourth OR element, the second input of which is connected to the output of the third address element AND, the output of the fourth matching element is connected to the information input of the communication channel, the output of the fourth element OR is connected to the second input of the element unequalities, the output of the higher bit of the address bits counter is connected 5 with the second inputs of the three output elements MeHixjB AND and the second input of the first OR element, the output of which is connected to the zero inputs of all the control triggers, the outputs of the first and second output elements AND, respectively, are connected to the first and second inputs of the OR element, output which b each address block is connected to the input of the same peripheral source, the output of the third output element I is connected to the input of the same name. peripheral receiver. Sources of information taken into account in the examination 1. USSR author's certificate No. 467341, cl. Q 06 P 3 / O2, 21.07.72. 2. USSR Author's Certificate No. 367445, KH ... Q 08 C 19/28, 15.About 70.