SU367445A1 - DEVICE PRIORITY ELECTION OF SUBSCRIBERS - Google Patents

Description

one

The invention relates to the field of telemechanics and can be used in information systems for various purposes with a time division of the channels.

There are known devices for electing subscribers in telemechanics systems, in which various methods of coding the subscriber's address are used, with a sequential polling of subscribers one by one for readiness for information exchange according to priority. The average election time for the exchange-ready and senior priority subscriber with the probability of readiness for any subscriber is N / 2 times the one-time election time, since an average of half of the subscribers need to be polled in order to select one exchange-ready subscriber.

However, in known devices, with an increase in the number of subscribers, the average time for a priority election increases in proportion to the number of subscribers.

The purpose of the invention is to increase the speed of the device.

The goal is achieved due to the fact that in the proposed device, the subscriber addressing units contain an address address counter, an address code generator, a control trigger, an unequal scheme, three AND schemes, a mismatch scheme, an OR scheme, and a driver,

The first and the first circuit are connected to the device input terminal, the nerve circuit output is connected to the control trigger input, the output of the mismatch circuit is connected to one of the circuit inputs OR, the output of which is connected to the inputs of the zeroing trigger and counter , the output of the second circuit "And connect to the input of the counter, the outputs of the counter are connected to the driver of the address code and to one of the inputs of the third circuit" And, the other inputs of the third and second circuits "And connected with the output of the control trigger and connected neravioziachnosti one of the inputs of the circuit, and through a shaper - to the other input ieravnoznachnosti circuit whose output is connected to another input "OR circuit, and the output of the third circuit" and connected to a terminal "output device. The block diagram of the device for priority election of subscribers is presented in FIG. I; A functional diagram of one of the priority addressing blocks is shown in FIG. 2; in fig. 3 image) 1Y signal plots in the characteristic points of the circuit device.

The device of the prioritized election contains a three-channel communication channel (Fig. 1), with the line / serving for transmitting the signal To the start of the election cycle, line 2 for transmitting the synchronization signals Tc, line 3 -

for signaling Ta. address code chosen by the senior priority of the exchange-ready subscriber. Signals of the start of the cycle of electing and synchronization are given to the inputs of blocks 4i, ..., 4i of the priority addressing of all subscribers.

All priority address blocks are completely identical in construction and wiring. The readiness signal from the corresponding subscriber is sent to the input of the block, and the output of the blocking signal is exchanged for exchange in the event of a vote.

Priority address block 4; serves to generate a sequential address code (the subscriber if the i-th subscriber is ready to exchange bitwise output of this course Hz to the accessible line 3, which performs the role of assembly, with simultaneous reception of the bits of the resulting code Zj of the address and to generate a signal to elect the subscriber based on the analysis of the current bits of the codes Jjj and Zj, where Xij is the / –th digit of the address code issued by the rth subscriber to the communication line; Zj is the / / digit of the address code in the line for the number N of abopents and the number of n address code bits.

The priority address block (Fig. 2) includes a shaper 5, an unequal scheme 6, an address code shaper 7, the first AND 8, a counter 9 bits of the address code, a second AND 10, a trigger 11, a third AND 12. mismatch scheme 13, scheme "OR 14.

A subscriber with a higher priority is assigned a higher address number.

The selection of the highest priority among subscribers who are ready for exchange is carried out as follows.

In the initial polarization, the trigger // and the counter 9 are in the zero state. For subscribers who are ready for the exchange, the signal arriving at the "Input block" terminal opens the "AND 8" circuits. At the initial moment of time, line 1 receives the signal G0 of the start of the election cycle. This signal sets the trigger 11 in a single state through the open circuit "And 8 subscribers ready for exchange"; Next, the And 12 and 10 schemes are opened. The non-ready for the subscribers exchange the Go signal through the mismatch scheme 13, 9 and the OR 14 scheme confirms the initial state of the // trigger and the counter 9. Next, only the ready-to-exchange subscribers work with the address blocks. The signals for synchronization of the address code bits coming from line 2 through the open circuit "AND 10 pass to counter 9, which changes its state, and through the address code generator 7 they generate successive codes Xid, Xc, ..., Xij,. .., Htsp-1} addresses of the corresponding ix subscribers.

Starting with a zero bit, the address codes arrive at the input of circuit 6 of inequality, as well as through shaper 5 to line 3, which plays the role of an assembly and in which obra-1

The signal Zj / A ,, -. Since the signal

i 0

Zj arrives at the second input of circuit 6, then

the output of the latter implements a failure signal (Yij Zi-j Xij. If the signal is Ug, then through the OR 14 scheme it goes to the installation of the trigger // and counter 9 to the initial state and the corresponding addressing unit

stops issuing the address code, i.e., the aboent is denied election. If the signal Yij is 0, then the priority addressing block continues to issue a serial address code of the subscriber to line 3. A code Z is generated on the line,

which corresponds to the address of the ready subscriber with the highest priority.

Upon completion of the code generation, the counter 9 of the addressing unit of the corresponding subscriber issues a select signal to the input of the circuit “And 12 and further to the terminal“ Output of the block. The subscriber's election time is / 1 log2A cycles, instead of N / 2 cycles with known election methods. Thus, the speed of election

increases N / 2 logzN times, which in systems with a large number of abopentov gives a significant gain.

An example is the operation of a priority election device from 16 subscribers (jV 16, / g 4).

If subscribers with addresses 1 (0001), 5 (0101) and 7 (0111) with the senior are ready to exchange, according to the address code, by subscriber 7 by priority, then the subscriber can be illustrated with signal plots

in fig. 3

At zero time, the signal Go sets the equipment of the addressing blocks to the initial state. At time t, from the first to the first, fifth, and seventh subscribers that are ready for election, line 3 will issue zero-bit addresses. Since dl, 5, 7, then Fi, o 0 dl, 5, 7. At time / 9 A) i 0; and Y5 ,, 0; Y, 0.

Since U), the first subscriber receives a refusal to elect. At the moment of time

/ 3 5.2 0, 7, and D5 ,, 7.2 0. BECAUSE 5 ,, THEN THE FIFTH subscriber receives a refusal to vote. There is one seventh subscriber who is elected. The code Zj corresponds to the code of the address of the SED, the eighth subscriber.

Subject invention

A device for selecting subscribers, containing addressing blocks, each of which is connected to a run cycle signal, an address bit synchronization signal line and a communication line, characterized in that, in order to increase the speed of the device, the subscriber address blocks contain a bit counter addresses, address code generator, control trigger, inequality scheme,

Three schemes "And, a mismatch scheme, schemes

The "OR and driver, and the inputs of the inconsistency circuit and the left circuit" And connected to the terminal "Device input, the output of the first circuit" And connection) to the input of the control trigger, the output of the mismatch circuit connected to one of the inputs of the circuit "OR, the output of which is connected to the inputs of the installation to zero of the control trigger and the counter, the output of the second circuit "And connect)) with the input of the counter, the outputs of the counter are connected to

to the driver of the address code and to one of the inputs of the third AND circuit, the other inputs of the third and secondary circuits of the AND circuit are connected to the output of the control trigger, the output of the address code driver is connected to one of the inequality circuit inputs, and through the driver to the other input of the unequality circuit, the output of which is connected to another input of the circuit, and the output of the third circuit is connected to the terminal “Output of the device.

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