SU647688A1 - Function generator - Google Patents

Description

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The image is in the field of specialized computing devices.

Converters of recalculation type II are known, in which a counter having a feedback circuit and a register in which the code controlling the conversion factor is written is used as a device with a variable conversion factor.

The disadvantage of these transducers is that, with high conversion precision, they require a baude. volume of equipment by increasing the size of the circuit elements. This, in turn, reduces the speed.

The closest to this technical solution is a device containing a c-bit input register, a logic block control unit and the first decoder, with the output (P - K) of the high bits of the input register connected to the inputs of the first decoder, the group of outputs of which

A characteristic task block is connected to the first group of inputs.

A disadvantage of the known device is its complexity.

The aim of the invention is to simplify the device.

The goal is achieved by the fact that the converter contains second and third decoders, a digital code generator and a comparator, and (n - k) most significant bits of the main register are made in the form of a reversible counter, and the low-order bits of the input register are connected to the first group of comparator inputs and through the second decoder with the second group of inputs of the characteristic setting block, the output group of which is connected to the first Input group of the logic block, the second group of inputs of which is connected to the third output group with the output group its chopper switch; output of the logic unit; Connected to the input of the control unit, the first output of which is connected to the counting input of the recloser counter; the second output — to the input of the digital code generator, the outputs of which are connected to the inputs of the T {5th decoder, the second group of inputs of the comparator the converter, the group of outputs of the reversible counter is a group of outputs of the higher bits of the prototype, the first and second outputs of the comparator are connected to the first and second control inputs of the right counter. The block diagram of the converter is shown in FIG. 1, the characteristic setting block diagram is shown in FIG. 2. The functional converter (Fig. 1) contains a P-bit input register 1, which includes the lower bits 2 and (c - k) high bits 3, made in the form of a reversible counter, a logic unit 4 consisting of elements AND, OR (no drawing is shown),, control block 5, first decoder 6, characteristic block 7, second and third decoders 8, 9, digital code generator 10, comparator AND, outputs lower than 12 and higher 13 bits of the converter. FIG. 2 denotes the elements OR 14, the elements And 15, typesetting field 16.. The converter works in the following way. The input number X is written to the input P-bit register 1, to the lower bits 2 and (n -K) high-order bits, made in the form of a reversible counter, the discharge states of which are decrypted by decoders 6 and 8 high and low bits respectively. The signal at one of the outputs of the decoder 6 determines the sign of the zone on the scale of the parameter being measured, which corresponds to the number to be decoded, X, and the signal at one of the outputs of the disinfector 8 determines, according to block 7, the lower half of the number, i (x) output, for example, linear characteristic. Depending on the value of the input number X at the output of one of the elements OR 14 (Fig. 2) of block 7, the permitting potential opens one of the inputs to the corresponding element AND of block 4. When the Start command is received, the control unit 5 starts the generator U of the digital code on the outs of which

Claims (1)

6,746,688 pvp numbers, for example, in increasing order of order. The generator output number U is decrypted by the decoder 9. If the signals coincide, act on the corresponding inputs of the AND blocks of the logic unit 4 from the decoder 9 and block 7, it will give a signal to the control unit 5, which stops the generator 10. In this case, the number written on the outputs generator 10 will be the lower bits of the output number i (4. The number recorded at the outputs of the generator 10 is compared in comparator 11 with the number written in the lower bits 2 of the input register 1. The result of comparing these two numbers is given to An actuator on one of the control inputs of the reversible counter 3. At the same time, the impulse from block 5 either does not change the state, counter 3, or adds or subtracts one in it. Thus, correction of the higher (U – U) bits of the input the numbers according to the result of comparing the lower races and thus the higher bits of the input number X are converted to the higher bits of the output number 1 (h). This completes the conversion process obtained by 4Kcnof (corresponding to the input number X used for the taring characteristic; presentation L is a composition K LSBs stored in the generator. 10 digital code, and (P-K) high-priority bits stored in the meter. The use of new elements and connections simplifies converter design, adjustment, testing and repair. A functional converter comprising a n-bit input register, a logic unit, a control unit, and a first decoder, the outputs (n-K) of the upper bits of the input register connected to the inputs of the first decoder, the output group of which is connected to the first group of inputs of the task unit harak .; Characteristics, characterized in that it contains second and third decoders, a Chi code generator 1 and a comparator, and (P - k) high-order bits of the input register are made in the form of a reversible counter, the outputs of the small bits of the input register are connected to the first group of inputs of the comparator and through the second decoder from the second group of inputs of the block a characteristic, the group of outputs of which is connected to the first group of inputs of the logical block, the second group of inputs of which is connected to the group of outputs of the third encoder, the output of the logic unit is connected to the input of the control unit, the first output of which is connected to the counting input of the reversible counter, the second output - to the input of the digital code generator, the outputs of which are connected to the inputs of the third decoder, the second group of comparator inputs OUTPUT and 5) of the converter bits, the group of outputs of the reversible counter is the group of outputs of the higher bits of the converter, the first and second outputs of the comparator are connected respectively to the first and second controls inputs of the reversible counter. Sources of information taken into account in the examination1. USSR Author's Certificate No. 372708, cl. Q 06 q 7/26, 1971. 2; USSR Author's Certificate No. 369589, cl. q 06 i 1/02, J.971. - L V fffff ig.gr-r