SU637824A1 - Discrete signal registering arrangement - Google Patents

Description

The invention relates to instrumentation engineering and can be applied to address search not even electrical circuits in automatic control systems. Devices are known for registering discrete signals and searching for them in the cities, where step finders are used as a switch. However, in these devices, the step finder has a low speed; in addition, to search for the address of a signal, it bypasses all points of the field to be tested. -NON and trigger, the first input of which is connected to the corresponding input of the recorder and the output of the first NAND element, and the second and third inputs of the trigger are respectively connected with one name by the trigger inputs of other switch channels, the output of the second NAND element is connected to the input of the third NAND element of the subsequent switch channel h. In this device, due to the need for sequential polling of the recorder channels, its speed is reduced. The aim of the invention is to increase speed. In the proposed device, this is achieved by the fact that a fourth AND-NOT element is entered into each switch channel, the first input of which is connected to the corresponding input x of the switch, the second input connects to the output of the third AND-NOT element, and the third input connects to the trigger the output of the fourth AND-NOT element is connected to the input of the first AND-NOT element and the second input of the AND-NOT element of this channel. The drawing shows a diagram of the proposed device. It contains the recorder 1, the multichannel switch 2, channel 3 of the discrete signal recording, trigger 4, the first 5, the second 6, the fourth 7 and the third 8 elements are NAND, respectively, and switch 2 has inputs 9, 92, .. “9 and outputs 10, South, ... the initial state of the device on all inputs 9 of switch 2 is logical. O, the triggers 4 are set to a state in which the inverse output is logical,

at the output of the element AND-NOT 7 - logical. Suppose that the inputs of the switch 2 receives signals in any combination, for example, inputs 9 and 92. Then the corresponding element 7 (the first input) is triggered and at its output a logical one appears, which prohibits the element 7g of the input7g via the AND-NI element. The signal of the O element AND -NE 7 of the input 9 is inverted and arrives at exit 10.

Thus, the switch circuit 2 permits only a single signal to be output.

In the registrar 1 of the signal address, this number is fixed and simultaneously a sync pulse is issued, which overturns trigger 4, removing the logical signal from the third input of the NAND 7 element - input 9). As a result, a logical output from the element AND-NOT b permits the appearance at output g of switch 2 of a logical one, which is registered similarly to the previous one, and then flip-flop 4 from input 9 occurs.

In this way, all the addresses of the post-trigger signals are recorded.

Similarly, register all the addresses that appeared at the inputs of the switch 2 signals in other combinations.

After all the addresses are registered, the device is reset to the initial position and the pulse is set to O.

The application of the invention makes it possible to determine the addresses of the incoming signals without sequential search of the controlled contact field.

Claims (3)

1. USSR author's certificate No. 450138, cl. Q05 B 23/02, 1974. 2. USSR author's certificate No. 443364, cl. Q05 B 23/02, 1973. 3. USSR author's certificate No. 466493, cl. (05 V 23/02, 1974.