SU637786A1 - Storage control block - Google Patents

Claims (2)

respectively, one of the inputs of which is connected to the output of the second element AND, the other input to the first control bus, the outputs of the fifth and sixth elements AND are connected respectively to the inputs of the second additional trigger, the first output of which is connected to the other input of the third element AND, the output of the second an additional trigger is connected to another input of the fourth element AND, the outputs of the third and fourth elements AND are connected via the OR element to the zero input of the main trigger. The drawing shows a functional diagram of the proposed device comprising a register i, main trigger 2, elements AND 3-8, element OR 9, additional triggers 10, AND, control bus 12, 13. The device operates as follows. Control signals determine the time of the beginning of the process of recording and shifting information in information processing devices (drives, chargers, etc.) and are fed through the first control bus 13 to the input of the register I and the single inputs of the trigger 2, 10. The second control bus receives pulses shift information in the accumulating line of information processing devices. In the initial state, trigger 2 prohibits the passage through the element 3 of information shift pulses to the information processing device. With the arrival of the control pulse, the trigger 2 is set to one state, allowing passage of the shift pulses through the element 3 to the accumulating lines of the information processing device. At the same time, when the control pulse arrives, the trigger 10 and the first bit of register I are set to one, and the pulse-shift arriving at the second input of register 1 is sequentially set to the next state, their bits. The previous bits of the register return to the zero state. At outputs 14, 15 of register 1, pulses are generated which are delayed relative to the control. The delay time of these pulses is determined by the number of bits between the input and the corresponding output of register 1 and the frequency of the shift pulses passed to register 1 .. The number of bits of register I between intermediate 5 and main 14 outputs of register 1 is selected so that the signal delay time in this section of the register, the repetition period of the control pulses following with a higher frequency was equal. An additional register output 16 is selected between the intermediate 15 and main 14 outputs and is an auxiliary output 16, which is necessary for the automatic operation of the automatic partitioning circuit (this is the control follow (x pulses. After a time equal to the repetition period of the control pulses, following with a frequency fi, the outputs 14 and 15 of the register} generate pulses that are fed to the inputs of element 4, as a result of which a signal appears at its output that switches the trigger 10 to the zero state. It arrives at the zero output of the trigger 10, permits the passage through element 5 to the zero input of trigger I of pulses arriving at elements 5 and 6 from the additional output 16 of register I. Through element 6 this impulse does not pass, since at that time it blocked the potential that is applied to the circuit from the single output of the trigger 10. The trigger 11 is transferred to the zero state and at its zero output a resolving potential is produced, which is fed to the element 8 and to the information processing device (or memory), in this case The accumulative rulers with a delay time (length) corresponding to the repetition period of the control pulses of the next frequency fi are turned on. In this case, the information processing device accumulates signals arriving at its input at a frequency synchronous to the frequency of the control pulses fi. A detection signal is generated at the output. Through element 8 and element OR 9, a control pulse generated at the output 15 of register 1 is applied to the zero input of trigger 2. With this pulse, trigger 2 returns to its initial state of the left and prevents passage of the pulse through the element 3 to the information processing device. The next control pulse, which comes from the bus 13 to the input of the register 1 and the single inputs of the flip-flops 2 and 10, transfers the flip-flop 2 to the single state, while the flip-flop 2 allows the flow of information shift pulses through the element 3 to the information processing device. Thus, the next cycle of accumulation of information is carried out. The resolving potential, which is developed in this case at the single output of the trigger 10, at the pulse frequency fi does not change the zero state of the trigger 11, since after each control pulse, starting from the second, the output of the element 4 produces pulses that translate the trigger 10 is again in the zero state, after which the zero state of the trigger 11 is confirmed by pulses arriving at its zero input from the auxiliary output 16 of the register 1. At a low tracking frequency fj at the output element 4 imps. are not produced. At the same time, a trigger 0, which is set to a single state by a control pulse arriving at its single input from the bus 13, does not change its state. In this case, the pulses that are generated at the additional output 16 of the register go through element 6 to the single input of the trigger 11 and transfer it to the single state. The resolving potential, which is produced in this case at the single output of the trigger II, is fed to the element 7 and on the information processing device; at the same time, in the information processing device, accumulative rulers are connected with a delay time (length) corresponding to the period of construction of control pulses that follow at a frequency f. The information processing device, in this case, accumulates signals arriving at its input at a frequency synchronous to the frequency of the control pulses fj. Element 7 and element OR 9 receive a pulse at zero input of trigger 2, which is generated at output 14 of register 1. This impulse transfers trigger 2 to the initial zero state, which prevents the passage of shift pulses to the information processing device until the next control momentum. The number of bits in register 1 between its input and outputs — intermediate 15 and main 14 — corresponds to the number of delay elements of each glowing line of the information processing device. The number of bits of the parts of the register and the parts of the accumulating lines of the information processing device is selected from the condition that the delay times of each of the parts correspond to the repetition period of the control signals. Therefore, the number of shift pulses passing through element 3 to the information processing device for each control signal is always strictly constant, equal to the number of delay elements of each accumulating bar of the information processing device and does not depend on the repetition period of the corresponding control pulses the repetition is longer than the passage of pulses through the corresponding part of the control register. Instead of the control register, other delay devices can be used, for example, a counter with decoders, etc. P |) meion e;) niogg) of the control unit () can automate the processing of information when the information processing device operates with several control signals, besides reliability of the information processing device, since communications are eliminated that need to be entered between the control unit, information processing device and external control devices during the manual control method and. A control unit for a memory device comprising a register, the first input of which is connected to the single input of the main trigger and to the first control bus, the second input of the register is connected to one of the inputs of the first And element and the second control, the other input of the first And element is connected to a single the output of the main trigger, the output of the first element I is connected to the output of the control unit, characterized in that, in order to expand the field of application of the control unit, the OR element is added to it, e triggers and elements And, one of the inputs of the second and third elements And connected to the first output of the register, the second output of which is connected to another input of the second and one of the inputs of the fourth elements And, the third output of the register is connected to one of the inputs of the fifth and sixth elements And The other inputs of which are connected to the zero and single outputs of the first additional trigger, respectively, one of the inputs of which is connected to the output of the second element I, the other input from the first control, the outputs of the fifth and sixth elements And soy ineny respectively to the inputs of the second additional flip-flop, a first output of which is connected to another input of the third AND gate, the second output of the second, additional flip-flop connected to another input of the fourth AND gate, the outputs of the third and fourth AND gates are connected via an OR gate to the zero input of the main trigger. Sources of information taken into account in the examination: 1, Kuzmin S. 3. Digital processing of radiocation information, ed. “Ow. radio, 1967. 2. USSR author's certificate number 428454, cl. G 11 C 19/00, 1974.