SU624296A1 - Associative storage - Google Patents

Description

This invention relates to the field of computing.

Memory devices (RAM) are known that simultaneously access multiple memory cells of the fio attribute. However, such devices have low speed and low fussational capabilities when solving information retrieval I1 extremal problems of a combinatorial type in real time.

The closest technical solution to the present invention is a memory device comprising a memory unit, an address counter, a control unit, the first output of which is connected to the first input of the memory unit, and a write-request register z. The main disadvantage of such a memory is the slow process of solving information retrieval and extremal problems, combinatorial, of the type, which is due to the large number of brute force operations and the inability to perform formation, allocation, sorting and

the emphasis of the subdivision for one calving addressing the contents of the memory.

The aim of the invention is to increase the speed of an associative memory device in solving information retrieval and extreme problems of a combinatorial type in real time.

This is achieved by introducing a command register, an output register, an input counter, an additional address counter, an address code switch switch, the poll register output register is connected to the first inputs of the Tfiznakov counter and a code commutator, and the register output is entered into the device. connected to the first input of the control unit, the second output of which is connected to the second input of the counter and the first input of the additional address and address counter, the output of the characteristic counter is connected to the second input to mmutatora code and the first input of switch addresses, additional address counter output is connected to

the third input of the switching module and the second input of the anjieca switch, the output of the address counter is connected to the third input of the address switch, the third output of the control unit is connected to the fourth inputs of the switch code and address, the output of the code switch is connected to the second input of the memory block, the output of the address switch is connected the third input of the memory unit, the first output of the memory unit is connected to the third input of the feature counter, with the fifth inputs of the code and address switches, with the second inputs of the additional address counter and the counter address , The first input of the output register, the second output of the memory unit is connected to the second input of the control unit.

The block diagram of the associative memory device is shown in the drawing.

It contains memory block 1, block

control 2, polling record register 3, command register 4, output register 5, feature counter 6, additional address counter 7, address counter 8, code switch 9, address switch 1О. Pam TI unit 1 CONSISTANTS with drive 11, 12, .13 and serves as the d: w markup of the incoming information array and internal communication addresses. The control unit 2 serves to control the operation of the associative memory device in the specified modes. Register polling 3 is designed to receive the information array from the outside. Command register 4 is designed to receive commands from the outside. Output register 5 serves to output the desired information array, subarray or word from an associative memory device. Characteristic counter 6 is designed to record the recorded characteristics on the address scale to provide information search mode. An additional address counter 7 is designed to accommodate the addresses of the first storage device 11 in order of increasing feature, in the second storage device. 12 in ordering mode. The counter of address 8 is designed to form an address in the mode of placement, storing the data and issuing information. The code switch 9 serves to organize writing to the memory 1 of the required code. The address switch 10 serves to generate the required address when accessing the memory block 1.

The associative memory device operates in three modes:

- record information array,

- ordering.

- search by; specified conditions, which include the following operations: search for phrases by attribute, issuing phrases by attribute, issuing i-th signs from the phrases zone by a given attribute, finding phrases with signs by a condition - a sign specified by the nearest attribute in the searched phrases, finding phrases with signs of min and morx, masking phrases, working with an array of phrases subjected to masking.

During the operation of an associative memory, the control unit 2 operates according to commands received from the outside through the command register 4 in the recording mode, and in ordering and searching, the control unit 2 generates commands independently, taking into account the signals coming from the accumulator. The control unit 2 generates code sequences that control the blocks that are part of the associative storage device in the recording mode, ordering and searching for information. In the recording mode, signals are sent to the blocks 3,4,8,9,10,11,12, 13, in the ordering mode — into blocks 6, 7, 8.9, 10, 11, 12, 13; and, in the search mode, into blocks 3,4,5,8,9,10,11,12,13.

Record mode information array.

Before recording, all blocks of the associative memory device are reset to the initial state by the Zero command. In the Record mode, the command enters the command register 4, is decoded by the control unit 2, and allows the input of the zero address from the address counter 8 via the address switch 1O to the accumulator 11. At the zero address, information on the input wires is entered through the input register of the polling 3 and the switch 9 to the zero 5th gate of the accumulator 11. Next, the series of control signals produced by the control unit 2 ensures the sequential search of the cells of the accumulator 11 and filling them with input information. After the input of the array of information is completed, the control unit 2 exposes on the readiness wires the readiness state of the associative memory device to the Forwarding mode.

Ordering mode.

Claims (3)

This mode involves a census in the accumulator 13 of the addresses of the accumulator 11 in order of increasing the value of the stored feature, and the addresses having the same attributes are placed in the accumulator 13 also in the order of increasing. Ordering mode is organized in the form of 6 1 investigators of viewing the contents of all the cells of the accumulator .1 1 and comparing the signs stored there with the counters of signs 6, All addresses that were found in the next viewing are recorded by the compact group into the accumulator 13. Character counter 6 after each view changes its state by one. The beginning of each new view is accompanied by writing to drive 12 at the address equal to the checked attribute, the address in drive 13, from which the next address group of drive 11 begins, where the additional address counter 7 controls the placement of drive 11 in orderly form in the drive 13 and changes its state with a hygienic detection of the phase containing the attribute that is currently being ordered. The ordering is completed after the number of views equal to the number of possible states of the trait. Simultaneously with the process described above, the characteristic, accumulator 12, is recorded in the discharge category of the presence of this characteristic in the array. The presence of a sign as a unit is recorded in the sign category at an address equal to the value of the sign to be checked. Search mode according to specified conditions. In this mode, information is received by wire of commands and numeric entry. The instructions contain information about the nature of the search (,,,) and the standard of comparison (characteristic value). The sign embedded in the instructions through the switch code 9 according to the commands of the control unit 2 enters the address part of the accumulator 12. The address part of the accumulator 12 performs the role of the sign scale. The cell of the accumulator 12, equal to the attribute, contains the starting address of the zone of the accumulator 13, where the numbers of all addresses of the accumulator 11 are located, having the specified sign. Simultaneously with checking the discharge of a sign, the signal on the readiness wires about the presence or absence of information with a given sign is formed in the control unit 2. A sign equal to one expands a series of control signals from control unit 2 to output register 5, and then to the output wires of a set of phrases that satisfy the character of the search; The proposed device makes it possible to increase the effectiveness of acs: sociative for 66 commemorative devices and the dsoto ability to solve information retrieval and extremal problems of the combinatorial type in real time. An associative memory device comprising a memory unit, an address counter, a control unit, the first output of which is connected to the first input of the memory unit, and a write-poll register, which in order to control the speed of the device, a command register is entered into it, output register, feature counter, additional address counter, code switch, address switch, with the register-poll register output connected to the first inputs of the characteristic counter and code switch, output of the command register register with the first input of the control unit, whose output is connected to the second input of the feature counter and the first inputs of the additional address and address counter, the output of the characteristic counter is connected to the second input of the code switch and the first input of the address switch, the output of the additional address counter is connected to the third input of the switch the code and the second input of the address switch; the output of the address counter is connected to the third input of the address switch; TpeTHJi the output of the control unit is connected to the fourth inputs of the switches to Yes and addresses, the switch code output is connected to the second memory block input, the address switch output is connected to the third memory block input, the first memory block output is connected to the third input of the characteristics counter, to the fifth inputs of the code switches to the address, to the second inputs An additional address counter and an address counter, with the first input of the output register, the second output of the memory unit is connected to the second input of the control unit. Sources of information taken into account in the examination: 1. USSR author's certificate number 407394, cl. G 11 C 15 / OO, 1973. 2. USSR author's certificate Ho 225927, cl. Q 11 C 15 / OO, 1908. 3. USSR author's certificate number 435563, cl. (t 11 C 15/00, 1974.