SU623256A1 - Arrangement for simulating errors in binary communication channel - Google Patents
Arrangement for simulating errors in binary communication channelInfo
- Publication number
- SU623256A1 SU623256A1 SU772448600A SU2448600A SU623256A1 SU 623256 A1 SU623256 A1 SU 623256A1 SU 772448600 A SU772448600 A SU 772448600A SU 2448600 A SU2448600 A SU 2448600A SU 623256 A1 SU623256 A1 SU 623256A1
- Authority
- SU
- USSR - Soviet Union
- Prior art keywords
- arrangement
- communication channel
- binary communication
- simulating errors
- simulating
- Prior art date
Links
Landscapes
- Catching Or Destruction (AREA)
Description
Случайна последовательность импульсов с выхода ограничител 2 подаетс на вход формировател 3. Яа выходе формировател 3 образуетс последовательность коротких импульвов ,сгруппированных по определенному закону. Эта последовательность импульсов поступает на триггер 4 со счетным входом, на выходе которого по вл ютс импульсы со случайной длительностью, распределенные по заданному закону.A random sequence of pulses from the output of limiter 2 is fed to the input of shaper 3. At the output of shaper 3, a sequence of short pulses is formed, grouped according to a certain law. This sequence of pulses arrives at trigger 4 with a counting input, at the output of which pulses of random duration appear, distributed according to a given law.
С выхода триггера 4 последовательность импульсо в различной длительности поступает на вход переключател 5. переключение выходов в соответствии с длительностью импульсов происходит так, что последовательность информационных символов либо проходит через инвертор 6, что обеспечивает имитацию искажений двоичных сигналов, либо пр мо проходит на From the output of trigger 4, a sequence of pulses of various duration is input to the switch 5. Switching the outputs in accordance with the duration of the pulses occurs so that the sequence of information symbols either passes through the inverter 6, which simulates distortions of binary signals, or passes directly to
выход 7 и на приемник 10 двоичных сигналов без искажений.output 7 and the receiver 10 binary signals without distortion.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SU772448600A SU623256A1 (en) | 1977-02-01 | 1977-02-01 | Arrangement for simulating errors in binary communication channel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SU772448600A SU623256A1 (en) | 1977-02-01 | 1977-02-01 | Arrangement for simulating errors in binary communication channel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SU623256A1 true SU623256A1 (en) | 1978-09-05 |
Family
ID=20694066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SU772448600A SU623256A1 (en) | 1977-02-01 | 1977-02-01 | Arrangement for simulating errors in binary communication channel |
Country Status (1)
| Country | Link |
|---|---|
| SU (1) | SU623256A1 (en) |
-
1977
- 1977-02-01 SU SU772448600A patent/SU623256A1/en active
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