SU618739A1 - Arrangement for comparing numbers in residual class system - Google Patents

Description

one

The invention relates to automation and computing, technology, and can be used to process data in automation and digital computing schemes that work in a system of residual classes ..;

A device is known for comparing numbers expressed in the system of residual classes, containing registers, adders, AND, OR,

NOT AND

The disadvantage of this device is that it allows you to establish only a match or a mismatch of two numbers in magnitude, but does not give an idea of their higher quality ratio (more, less).

The closest in technical essence to the invention is a device for comparing the number in the system of residual classes, containing adders, elements AND, the element NOT, registers, a comparison circuit and h analysis nodes, each of which consists of an adder, register, comparison circuit, elements AND, OR, and the outputs of the register are connected to the inputs of the comparison circuit, the adder and the first element OR, whose output is connected to the first input of the AND element, the output of which is connected to the control input of the adder, whose information outputs are connected enes to inputs

the register, and the control output to the first input of the second OR element, the output of which is connected to the control input of the comparison circuit, the analysis node.

The disadvantage of this device is low, speed, due to the fact that to obtain the result of the comparison it is necessary to spend a number of cycles equal to

the absolute value of the largest number.

The aim of the invention is to improve the speed of the device. To do this, the device outputs

Claims (2)

of the first elements OR of all nodes of the anadzhz are connected to the inputs of the first element AND, the output of which is connected to the first input of the second element AND and through the element NOT to the first input of the third element AND whose output is connected to the control input of the first adder, and the second input to the output of the circuit comparison, the inputs of which are connected to the outputs of the comparison circuits of all analysis nodes, the output of the second element I is connected to the control input of the second adder, the outputs of which are connected to the inputs of the first register, the outputs of which are connected to the input The second adder, the control input of the third adder is connected to the output of the comparison circuit, and its information outputs are connected to the inputs of the second register, which is connected to the inputs of the third adder, the outputs of the first register are connected to the inputs of the first adder Comparison circuits are connected to the second inputs of the elements AND of all analysis nodes, and the second inputs of the IGO elements of all analysis nodes are connected to the control bus of the device. The drawing shows the functional scheme on the device. The device contains, annodes nodes 1 h 2 and consisting of adders 2, 2jji. . ..2, comparison schemes 3, 3,.;. 3, registers 4, 2 elements AND 5, 5g ... Зц, elements OR 6, 6, ... 6,. Elements OR 7, f, 7j, ... 7, the sum of the tori 8-10, registers 11 -13, element AND 14-16, comparison circuit 17, element HE 18, control bus 19. The device works as follows. By the start of the comparison, the registers 4 |, 42, ... 4) are written down as compared numbers. After being switched on by the bus 19, the OR or gt .. "bc elements are used to determine the numbers Л", ", ... K w" A and overwrite them in the comparison circuit 17. The comparison circuit 17 determines the minimum of these numbers (f ") And gives its value to the subtractive inputs of adders 2, 2, ..., 12 through 5t1sryy-elements And 5, 5, ..., 5 c. The value of | n is subtracted from all compared numbers. At the same time, the value of m from the output of the comparison circuit 17 is fed directly to the input of the adder 8 and through the open element I 15 to the input of the adder 10. After retrieving the value from all the compared numbers and adding this value to the registers 11 and 12, the adders 2, 2, .. ., 2f | setting the zero state and the control signal from the outputs of the adders 2, 2y, ..., 2 through the corresponding elements OR 6 f € 2f .... 6n goes to the inputs of the registers 3, .32 /: ..., 3 .ni permitting the implementation of the following. In the sleep cycle, the determination of r „“ for the compared numbers, reduced by the value of Ksch, the choice of the values of l, Pmax, -Wi, subtraction of the value of r from the Numbers and its addition to the registers 11 and 12, occurs. The subtraction process continues until one of the numbers will not become zero. In this case, a single signal at the output of one of the elements OR 7, Tg, .... / p will disappear, as a result of which one of the elements AND 5, 5g, ... 5, will be closed, and / also the elements AND 14 and 10, and will open the element And 16. In the register will be written down the smallest of the compared numbers. In the process of the subsequent subtraction of m from the compared numbers, this value is added to the register 13 through the now open signal from the output of the element HE 18. An element and 16 is still added to the register 12. The process continues until then. ca the largest of the numbers will not become zero. In this case, the cycle of operation of the device ends. As a result, the largest number is recorded in register 12, the difference is maximum in register 13. Apparatus of the Invention A device for comparing numbers in a system of residual classes containing adders, elements AND, element NOT, registers, comparison scheme and M analysis nodes, each of which consists of an adder, register, comparison scheme, elements AND, OR, and the outputs of the register are connected with the inputs of the comparison circuit, the adder and the first OR element, the output of which is connected to the first input of the AND element, the output of which is connected to the control input of the adder, whose information outputs are connected to the inputs of the register, and the control output - to the first input of the second OR element, the output of which is connected to the control input of the comparison node of the analysis node, characterized in that, in order to increase the speed of the device, therein the outputs of the first OR elements of all analysis nodes are connected to the inputs of the first AND element whose output is connected with the first input of the second element I and through the element NOT with the first input of the third element I, the output of which is connected to the control input of the first adder, and the second input to the output of the comparison circuit whose inputs are connected to the outputs of circuits All the analysis nodes, the output of the second element I are connected to the control input of the second adder, the outputs of which are connected to the inputs of the first register, whose outputs are connected to the inputs of the second adder, the control input of the third adder is connected to the output of the comparison circuit, and its information outputs are connected the inputs of the second register, the outputs of which are connected to the inputs of the third adder, the outputs of the first adder are connected to the inputs of the third register, the outputs of which are connected to the inputs of the first adder, the output from Comparison circuits are connected to the second inputs of the elements AND of all analysis nodes, and 9 second inputs of the JOS 1LC of all analysis nodes are connected to the control bus of the device. Sources of information taken into account in the examination: 1. The author's certificate of the USSR 242435, class .06 R7 / 04, 05.13.69. 2. Authors certificate of the USSR 234003, cl. G06 F 7/04, 04.02.69.