SU612287A1 - Arrangement for checking permanent memory units - Google Patents

Description

(54) DEVICE FOR MONITORING THE UNIT €) IN PERMANENT MEMORY

This invention relates to memory devices.

A device for monitoring fixed memory blocks is known, comprising a register with a counting input, a checksum setting unit and a comparison circuit (I). Monitoring 14 Information with the help of such a device is carried out by comparing the sums of all the numbers contained in the device modulo two with a pre-calculated constant.

A disadvantage of this device is the low control accuracy and the complexity of determining the address of the blinker. .

Of the known devices, the closest to the technical solution proposed is a device for monitoring fixed memory blocks containing an address register connected via an address decoder to the output of a device whose input is connected to an adder connected to a control unit via a number register (2J. the device automatically controls the blocks of permanent memory modulo three n. cyclic sum, formed by summing all the memory blocks contained in the memory block with transfer of the overflow unit from the highest time. p yes to junior.

The disadvantages of this device are the omission of a certain type of error (incorrect distribution of information by addresses, rearrangement of parts of information in places,

mutually compensating errors) and a decrease in the accuracy of control in the absence of the number of control codes modulo three.

The purpose of the invention is to increase the accuracy of the control.

The goal is achieved by the fact that the device for monitoring the memory blocks contains a block for setting summation cycles, the inputs of which are connected to the outputs of the address register and the control block, respectively, and the outputs to the inputs of the accumulator and control block.

This makes it possible to read the numbers from the constant memory block several times, each time forming a new checksum, and comparing the sums obtained with the check constants.

The drawing shows a block diagram of the device.

The device contains with triggers the address register I, the address decoder 2 connected to the checked memory block 3,

numeric register 4, adder 5, control unit 6 n block 7 assigning cycles of summing 7 whose inputs are connected respectively to the outputs of the register of address 1 n of the control unit 6, and the outputs to the inputs of the adder b and block are controlled 6.

The checked block of permanent memory 3, in addition to the monitored numbers, additionally contains check constants with which the control is carried out. Constants are either cyclic sums or modulo two sums. The number of control constants depends on the volume of the storage unit and on the possible number and peculiar errors caused by the design features and manufacturing technology of the unit. For example, the first control constant is the cyclic sum of all numbers. The second control constant is the cyclic sum of the numbers obtained by cyclically shifting to one side of each successive number read from the fixed-memory block relative to the previous one by P | bits The third control constant is the cyclic sum of the numbers obtained by cyclically shifting to one side of each successively read number of the previous previous by PG, and so on. The adder 5 is designed to obtain cyclic checksums or modulo-two sums. To obtain the second, third, etc., checksums, adder 5 has cyclic shift circuits that are controlled by block 7 for setting the cycles of the summation. The adder 5 has an indication that permits monitoring of the block of permanent memory 3 in the absence of control constants in the latter. The unit 7 of the task of summation cycles is intended for organizing the second, third and subsequent summation cycles in which pulses are generated of the cumulative shift of the contents of the MaTopai 5 sum by ni bits in the second summation, on Pa bits in the third summation, etc. The control unit G is designed to generation of output signals (standard signals), for organizing the operation of the control device and has controls for switching modes of operation.

The device in automatic mode works as follows.

Under the control pulses of control unit 6, the address register I generates consecutive addresses. In the checked block, the permanent memory 3 is sequentially read to the numeric register 4 numbers according to the worked out addresses. Each number is then sent to the adder 5. The cyclic shift pulses during the first summation are not generated. After summing up all the numbers, the overflow signal from the output of the trigger 8 of the most significant bit of the address register I is fed to the input of block 7 of tasks

CYCLES summation and control unit 6. One output of block 7 permits the passage of the shift signals of adder 5 generated by control unit 6 during subsequent summation cycles, and the other output of block 7 determines the number of shift pulses produced by control unit 6 depending on the number of the summation cycle. The overflow signal control unit generates signals that compare the result of the summation with the corresponding control constant. If the control results are positive, the control unit 6 generates signals to form a second checksum, but before each number is sent to the adder 5, the contents of the latter are cyclically shifted to the same side by P | bits, determined by the output of block 7, the task of summation cycles, in the next cycle of summation, the contents of the adder are shifted by n 2 bits, and so on. At the end of each cycle, the obtained sums are compared with KOHCI. In case of negative comparison results, the signal "Stop." After the operator has recorded the differences in the amount received from the constant, the verification continues until all checks are completed. After the completion of the last cycle of summation, the unit 7 of the task of summing cycles through the control unit 6 generates a "Stop" signal, while if all the obtained sums coincide with constants, the control unit 5 generates the signal "OK.

Since each number is assigned a certain shift constant, which depends on the address of the number, errors that are wrong in the incorrect distribution of information by addresses will be detected. Most of the errors that are mutually compensated by the usual cyclic summation are also detected.

Claims (2)

Invention Formula A device for monitoring fixed memory blocks containing an address register connected via an address decoder to an output of a device whose input is connected via a number register to an adder connected to a control unit, characterized in that it contains a task block to improve control accuracy summation cycles, the inputs of which are connected to the outputs of the address register and the control unit respectively, and the outputs to the inputs of the adder and the control unit. Sources of information taken into account in the examination; S. Copyright certificate I 235108, M.cl. G 29/00, 1967. 2. Information leaflet No. 101-73 Ulnovsky TSNTI.