SU590861A1 - Discrete device for clocking - Google Patents

Description

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The invention relates to the transmission of discrete information and can be used to extract a clock frequency from a received signal.

A discrete clock synchronization device is known that contains a serially connected controlled frequency divider, a phase discriminator, a first reversible counter and a second reversible counter, the input of which is connected to the first control input of the controlled frequency divider and a frequency divider whose output is connected to the second control input controlled frequency divider 1.

However, the known device is characterized by a long synchronization time.

The purpose of the invention is to reduce the synchronization time while maintaining accuracy and noise immunity.

To do this, a discrete clock synchronization device containing a series-connected controlled frequency divider, a phase discriminator, a first reversing one, a counter and a second reversing counter, whose input is connected to the first control input of a controlled frequency divider, and also a frequency divider whose output is connected to the second control input of the controlled frequency divider, serially connected interlocking element is introduced.

additional controlled frequency divider, additional phase dnscriminator and element And, the input and output of the second reversible counter connected to the inputs of the blocking element, and the output of the element And through the frequency divider connected to the first control input of the additional controlled frequency divider, the second control input of which The output of the first reversible counter, and the second input of the additional phase discriminator are connected to the input of the phase discriminator, and the controlled divider is often you, the second input of the AND element and the third control input of the additional controllable frequency divider are fed into the reference signal.

The drawing shows a structural diagram of the proposed device. The discrete clock synchronization device contains a series-connected controllable frequency divider 1, a phase discriminator 2, a first reversible counter 3, and a second reversible counter 4, the input of which is connected to the first control

the input of the controlled frequency divider 1, as well as the frequency divider 5, the output of which is connected to the second control input of the controlled frequency divider 1, connected in series by the blocking element 6,

Additional driving controlled frequency divider 7, additional phase diocryglinator 8 and element 9, the input and output of the second reversible counter 4 connected to the inputs of the blocking element 6, and the output of the element I through frequency divider 5 connected to the first control input of the additional control divisor 7, the second control lush, whose input is connected to the output of the first reversible counter 3, and the second input of the additional phase discriminator 8 is connected to the input of the phase discriminator 2, while the controlled divide Only 1 frequency, the second input of the element AND 9 and the third control input of the additional controlled frequency divider 7 are fed into the reference signal.

The device works as follows.

In the absence of frequency detuning, an additional controlled divider 7 synchronously with a controlled divider 1 frequency monitors the phase of the clock frequency of the received signal. Therefore, on average, to the input of the second reversible counter 4, the signals of two opposite half-fold characters corresponding to the phase mismatch symbol pass equally often and alternately, so that they do not pass to the output of this counter. In the presence of frequency detuning, this equilibrium is disturbed, and from the output of the first reversible counter 3, the signals of one of the signs arrive more often, the human signals of another sign. Signals of the corresponding sign are passed to the output of the second reversible counter 4 and then through the blocking element b to the input of the additional controlled divider 7, changing the phase of the additional controlled divider 7, as a result of which its phase becomes different from the phase of the first controlled divider 1 frequency. The additional phase discriminator 8 generates signals corresponding to the detuning sign with a following frequency equal to the nominal clock frequency and proportional to the phase difference of the controlled dividers 1 and 2 as a result. As a result, the reference frequency pulses are allowed to the frequency divider 5 input through the element and 9.

At the same time, the frequency divider 5 periodically leaves pulses, the frequency of which is proportional to the phase difference of the controlled dividers 1 and 7, and therefore the frequency detuning that is currently detected. The output of frequency divider 5 is an alignment signal.

The inputs to the control outputs of the controlled dividers 1 and 7, the adjustment pulses change their division ratio, and the detuning of the detuning frequency, resulting in slowing down and then stopping the output

pulses from the second reversible counter i and the phase of the additional controlled divider 7 ceases to change relative to the phase of the controlled divider 1 frequency. Equilibrium is established in the system.

The blocking element 6 accelerates the process of adaptation to the frequency detuning, since after the output of a signal of a certain sign from the second reversible counter 4, i.e. after

As the frequency detuning sign is determined, the blocking element b passes to control an additional divider 7 signals of the same sign directly from the input of the second reversible counter 4, as if turning off the averaging (integration) of the signals of this sign until the output of the second reversible counter 4 appears . The proposed device can shorten the synchronization time.

Claims (1)

Invention Formula Discrete clock synchronization device containing serially connected controlled frequency divider, phase discriminator, first reversible counter and a second reversible counter, the input of which is connected to the first control input of the controllable frequency divider, as well as a frequency divider, the output of which is connected to the second control input of the controlled frequency divider, in order to reduce the synchronization time while storing accuracy and noise immunity; a series-interlocking element, an additional controlled frequency divider, an additional phase discriminator and an AND element are introduced, the input and output of the second reversing counter Connected to the inputs of the blocking element, and the output of the element AND through the divisor frequency is connected to the first control input of the additional controllable frequency divider, the second control input of which is connected to the output of the first reversible counter, and the second input is up to the phase discriminator is connected to the input of the phase discriminator, with this controllable frequency divider, the second input of the AND element and the third control input of the additional controlled frequency divider reference signal is given. Sources of information taken into account during the examination 1. M. P. Romanovsky. Astatic discrete synchronization system. “Radio engineering, Vol. 23, AB 3, 1968, p. 31-38.