SU577491A1 - Processor for digital processing of signals - Google Patents

Description

These KoadxbimsieHTbi for the number of points iV rao are read in advance in the number and storage time; Oh; in RAM, in each iteration of dp calculations using formulas (1), the values of trigonovic coefficients are needed in an amount depending on the number of the iteration being performed: by defining it is one value, in the second - two, in the third - four, etc., in the last iteration it is necessary to read all the values of the trigonometric fitsientoB from the operational memory. In a known processor, the control circuit for reading the trigonometric coefficients fixes the state in which to calculate the next pair of points, it is necessary to use the new value of the trigonometric coefficient read into the buffer registers from the RAM in the previous cycle of changing the three-factor coefficient. At the specified time, the trigonometric coefficient value transfers from the buffer registers to the multiplier registers of the arithmetic unit operand from the operative memory to the buffer the first registers reads the next value of the coefficients and starts the cycle of calculating the next pair of points. The disadvantage of the described processor is 5 t5151. With the necessity of introducing into it y buffer registers with control logic for writing — reading information — which leads to an increase in the circuit equipment and a decrease in the reliability of the processor. The aim of the invention is to increase the reliability of the processor. This is achieved by the fact that, in the proposed processor, the control circuit for reading trigonometric coefficients contains two stages of OR circuits, the second cascade is combined in the outputs by the AND circuit, the outputs xpuriepOB of the iterative slide register are randomly connected to the inputs of the OR circuit of the cascade together with ; OR is the lowest-order bit, and the outputs of the circuits OR of the first cascade and the trigger of the a / tsees operand counter are bitwise connected to the inputs of the circuits OR of the second cascade. In this case, the control circuit for reading trigonometric coefficients fixes the cycle, preceding the cycle of calculating a pair of points, for which a new value of the trisometric coefficient is needed and ensures synchronization of the reading of triggers |) 1 coefficients from the operative memory of the arithmetic device of the operands. Assuming this, the need for buffer registers and control logic associated with the NCMS is falling, which substantially reduces the bandwidth of the circuitry and increases the reliability of the processor. Fig, 1 shows a block diagram of the proposed processor; in fig. 2 is a block diagram of an address arithmetic unit; in fig. 3 is a control circuit for reading trigonometric coefficients. The processor contains a random access memory 1, an arithmetic unit of operands 2 and an address arithmetic unit 3., An address arithmetic unit 3 contains an address counter for operands 4, an iterative shift register 5, an address counter for trigonometric coefficients 6 and a read control circuit, trigonometric coefficients 7, a read control circuit trigonometric coefficients 7 for the case of, for example, a four-bit (four-bit) address, contain an IL-circuit 12,13,14,15 of the second stage, o The AND 16 combined outputs of the outputs, the control circuit for reading trigonometric coefficients of dp addresses with higher resolution, is constructed similarly to the one shown in FIG. 3 by adding one two-input circuit for each stage and the OR circuit and adding one input to the AND circuit for each additional double address address, input, trigger 17,18,19,20 of the iterative shift register 5 are connected to the corresponding inputs of the circuits OR 8,9,10, 11, to the second inputs of which are connected the outputs of the circuits OR the neighboring younger bits of the outputs of the circuits OR 8, 9.1 0.11, connected & respectively to the inputs of the circuits OR 12, 13,14,15, to the second inputs of which; The trigger outputs are 21,22,23,24, the corresponding counts of the addresses of the operands are 4, Every time in the I -th iteration, the unit state at the output of the AND circuit indicates the need to read the new trigonometric coefficient into the registers of the multiplier of the arithmetic unit of the operands. Using the above control scheme by combining trigonometric coefficients in the proposed processor, the readout of trigonometric coefficients directly into the working registers of the arithmetic unit of operands, which eliminates in the processor a buffer register with the control logic that is used in practice, and this

inaeT ooem schema oooraivivann and poiiiiuKiT Reliability of the processor.

F and r mula n 3 about b and t e and and

ilfioncapes the fact that, with and (ly of the CPU reliability, the reading control scheme of the trigonometric coefficients {) {) of the patients is written out in the form of two stages of OR circuits, the second The shell is combined with the outputs of the AND scheme, the steps of the iterative shifts of the register are connected to cx inputs (m OR of the first cascade together with the output of the OR circuit of the next-low-order bit, and the outputs of the OR circuit of the cascade and three: the operand address counter bitwise connected to the inputs of the circuit OR BTOpoJo cascade.

Sources of information taken into account in the examination:

1, USSR Author's Certificate No. 51О948, cl. G 01 V 1/28, 1976.

2. US patent N9 3517173, CP. 235156, 1970

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