SU571901A2 - Device for decoding linear codes - Google Patents

Description

one

The invention relates to telemechanics and communication technology. It can be used when designing decoding yci solutions for channels with error correction.

Devices for decoding linear codes are known, comprising a receive register, a modulo-two adder, a switch, and a threshold element.

These devices use a threshold element with a hard threshold value, so all characters are decoded with the same degree of fidelity.

It is also known a device that performs character-by-character decoding, taking into account the importance of certain characters. Expansion of the functionality of this device is achieved by the introduction of a binary counter, the counting input of which is connected to the output of the modulo two adder, a decoder, whose inputs are connected to the bits of the counter, and the outputs are combined through the elements OR in accordance with the threshold values for decoded characters defined by code structure. The output of each element OR is connected to the input of the corresponding matching element.

This device does not fully realize the ability of the code to correct errors.

The purpose of the invention is to increase the faithfulness of error-free decoding — it is achieved in that the device containing a binary counter, a decoder, a modulo two adder, the OR elements, a key, is entered with an additional shift of the HESTP, whose input is connected to the corresponding input of the device, and the inputs of the bits of this register are connected to the input of a modulo-two adder through additional shreds.

The drawing shows a structural diagram of the device.

Claims (2)

The device contains a receive register 1 switch keys 2-13, an adder 14 modulo binary counter 15, decoder 16, elements OR 17, 18, input buses 19, 2O, match elements 21, 22, output buses 23, 24, and shift register 25. The essence of the sentence is illustrated by the example of a device for decoding a linear (10.4) code that allows ortho nalisation. For example, let the checking symbols bj, b, b be given by linear combinations of information symbols a, a, a «I a. (here is the addition of Du modulo two) C "2 + Ц C-O | Qj L Oj and bg- Oj + O, Oj a, bj-04 + a For each information symbol, you can create a system of separated checks: Oj- a 2 Oj Oj, + bj "i bi a, Oz + C a, -" I Oji + b. “Г bg + b Og bj +“ З-а 4 - 04 Oj-ai + bg + ba Oj Oj + b Information symbols can be divided into two coarse validity ratios by the number of verification ratios. Symbols of the first group and Qj can be found in five different ways, i.e. unmistakably decoded w | z errors of multiplicity 4 2. Accordingly, the symbols of the second group a and Og can be correctly identified only for any single-level error, i.e., less reliably but with the symbols of the first group. The device according to the principle of operation is a synchronous automaton. Harbor tires and readouts are shown in the drawing. devices conveniently run irpiffiaTb in cycles. In the initial position, the decoded uoa OfO Of Oib -b aanacmo layer into register 1 (from the right Q. on the left}, the key is closed "is closed according to a rigid program defined by the associated checker corresponding to 1st. At the first bar, the key 2 is closed O. (possibly, distorted), connects to one of the inputs of the matrix 14. On the second (m "| tact key 2 is opened, the keys 3 and 6 are closed, which are connected to the inputs of the adder of the symbol 92 and b |. On the third the keys 3 and 6 are opened, and the keys 4 and 7 are closed, which connect the characters a, bj, etc. to the inputs of the adder & The a wave, taken from the adder 14 on each clock, enters the counter 15. On the fifth clock cycle and the counter is written down the number of single characters of t, & the output corresponding to this is excited by the decoder 16. The decoder outputs corresponding to the numbers 5, 4, 3 at its input, are combined by the OR element 17, and the corresponding numbers 3 and 2 are the OR element 18. At the same time, the performance signal is also sent to the bus 19 and the resulting value of the symbol a is removed from the output bus 23, Except In addition, the value of this symbol It is written into a register register 25. Thereafter, the counter 15 is brought to the zero state, and a similar decoding cycle starts, CHMBOIl Qj. The value of the symbol a is also eventually written to the shift register. The symbol a. it shifts to the left (in the drawing). The symbols Qa and Q. are decoded in three ticks (by number, check ratios). The test relationships for these characters include the characters o. and si a Their values in the proposed device are removed from the steps of the bits of the shift register and nt are given through an additional group of keys 12 and 13 of the switch to a Modulo two adder. The execution enable signal in this case is fed to the 2 O bus, and the resulting values of the symbols d and otj are removed from the output bus 24. Thus, to decode the symbols a and 01, the values of the symbols O and o2 are not from the receiving register (as is done in the prototype ), the ac output of the device corresponding to the characters a, and 0g (possibly corrected). This increases the likelihood of correct decoding of the symbols a and Ot. (hence, the whole word), so as the result of decoding is not affected by the additional combineries (errors in the input word, HanpHMep, o (ja2., a, oi, of, b4. ad1s2: id.-Rprototype This kind of Pschvodt errors for decoding one yy of both 0YMBOLS a J and dI In the example above, the decoder output corresponding to the number three at its input is common to both OR elements. However, the output signal will be taken from only one output bus , depending on whether the performance resolution signal is sent to the KaKjTo from the input buses. rmula izo.breteni apparatus for decoding of linear codes by the authors. binding. № 514435 ,, characterized in that in order to increase the probability of error-free decoded. 56 Inputs (additional keys are entered into it | and the bits of this {yugistr) are entered via a shift and shift register, the input of which is noif additional keys are connected to the input of keys to the corresponding output of the modulo-adder two. 571901