SU562791A1 - Chess Clock - Google Patents

Description

arrive at the circuit 2 synchronization, generating clock pulses, providing addressing information block 10 storage registers and coordination in time of operation of all devices.

The synchronization circuit 2 is constructed so that the 5 decimal places counter produces ten consecutive time intervals, each of which contains three time intervals of the 4 channel counter (the first interval is the state for counting the white time, the second black, and the third order number of the move). Each of the latter, in turn, is divided into four intervals - the state of the 3 binary bits counter, forming an information tetrad in the binary-decimal course.

When the on-off key 6 is pressed, the information unit (the first state of the 3-bit counter) is recorded in the white time interval (the first state of the 4-channel counter) in the first decimal digit of the 5-bit counter. This moment of recording is organized by the input scheme 7.

Then, the unit of information, passed by the adder 8 and the transfer circuit 9, is recorded in the blocks of the 10 storage registers, where it is delayed until the end of the first synchronization cycle, which is equal to one second.

At the beginning of the second synchronization cycle, the unit re-enters through the information input circuit 7 and the unit from the storage register of block 10 to the adder 8, at the output of which a deuce is obtained, which, having passed the transfer circuit 9, is again recorded in the storage register of block 10, etc. only at the output of the adder 8 is obtained ten, the transfer circuit 9 is triggered and a unit of information is transferred to the second time interval of the counter 5 decimal places. In the same way, transfer and other decimal places. At two decimal places the transfer is performed then-lg., When the sum is equal to the thrash. The time count of the white channels is performed until the on-off key 6 is pressed again, then the information is recorded in the time countdown interval (the second state of the 4 channel counter) in the first decimal place. Further, the time count of the black channels occurs around the ring: adder B, transfer scheme 9, block 10 storage registers. At the same time, the information of the white channels is stored in its own time interval, regardless of the change of the information of the black ones.

The counting of the sequence number of the stroke occurs in the third state of the 4 channel counter. Unlike the first two states — the channels in a given state, a unit of information is not recorded in each cycle, but only after pressing a two-position key that includes the “white” channel. This is organized by the input scheme 7.

To enable display

5 and printing the time of the white and black channels and the number of the progress information from the adder 8 is fed to the output register in the sequential code. On the setter 12 a pre-set play time is established,

after which the buzzer turns on.

Claims (2)

1. USSR author's certificate No. 390499, M, Cl.2 G 04 F 7/00, 1973. 2. USSR author's certificate Jxfo 450129, M. Kl.2 G 04 C 3/00, 1974.