SU560218A1 - Pulse synchronization device - Google Patents

Description

one

The invention relates to the field of computational technology and can be used in multichannel automatic control and regulation systems.

A device for synchronizing pulse signals is known, which contains triggers, differentiating elements, isolation diodes, AND elements, contact groups.

A disadvantage of the known device is the loss of information during the simultaneous operation of contact groups, which limits the areas of its possible application.

Another known device for synchronizing pulsed signals contains in each channel triggers, AND, NOT, and majority elements 2.

Its disadvantage is the impossibility of processing signals from several independent sources.

The closest to the invention to the device for syncronization of pulse signals contains a generator of clock emulsions, triggers, elements AND, element OR, the output of which is the output of device 3.

The disadvantages of this device are its complexity, associated with the presence (in addition to non-elemental elements) of the delay lines, the counter and the scheme of actisoviadia.

and the possibility of false positives, the probability of which increases with increasing duration of input pulses.

The purpose of the invention is the protection of the device and the improvement of its operational characteristics.

This is achieved by the fact that in each channel a single input of recording trigger is connected to the corresponding information and device input, the single outputs of trigger, storage and reset trigger to the first inputs of the first, second and third elements And, the second inputs of which are connected to the corresponding outputs of the clock pulse generator . The output of the first element AND is connected to the single trigger input, stored, the output of the second element AND to the single input of the reset trigger, the output of the third element AND to the zero inputs of the trigger and the storage trigger. The zero input of the reset trigger is connected to the second input of the AND element, the outputs of the second AND elements of all channels are connected to the corresponding inputs of the OR element.

Diagram of the device shown in the drawing.

It consists of n channels. Each channel has trnggers 1, stored 2 n reset 3, nx single outputs but not connected to the I011VYM inputs of the elements 4, 5, 6, respectively, the second inputs of the elements H -

to outputs 7g, & i, 9-; (- channel number) generator 10 clock pulses. The single inputs of recording triggers are connected to the corresponding information inputs I (r 1-tl), the outputs of the second And elements of all channels are connected to the corresponding inputs of the OR element 12, the output 13 of which is the output of the device.

The device works as follows.

The initial state of triggers 1 and 2 is zero. The impulse arriving at input 11 ,, sets the recording trigger in the i-th channel to position "1", and the potential signal from the single output of trigger 1 is fed to the first input of the And 4 element. When (the second input of the And 4 element of the first clock pulse output 7j of generator 10, storage trigger 2 is set to state "1, reset trigger 3 remains in state" O, and a potential signal from trigger output 2 is sent to the first input of element 5. When the second input of element 5 comes from the clock pulse from output 8, generator 10 impulse from the output Yes, the element AND 5 is fed to the corresponding input of the element OR 12 and further to the output 13 of the device. The potential signal of the trigger 3 is fed to the first input of the element AND 6, therefore at the moment of applying the third clock pulse from the output 9j of the generator 10 pa the second input of the element 6 is generated setting the initial state of the triggers 1, 2.

The clock pulses of the same series of different channels may overlap and coincide, except for the pulses of the second series (at outputs 8), which must be spaced in time.

The proposed device favorably differs from the known one, since it excludes the probability of a false response at any mutual timing of the input and clock pulses, and moreover.

There are no delay lines and anti-matches By connecting to the output of the device, for example, an adder on a reversible counter, you can implement summation modes or

subtracting the number of pulses, with asynchronous information flows entering the synchronous computing system via any number of information channels.

Claims (3)

1. Auth. St. No. 325605, cl. G 06F 3/02, 1969. 2, Auth. St. No. 378830, class G 06F 1/04, 1971. 3. Avt. St. No. 224898 “and G 06F 1/04, 1967. Channel f2) . 11s. Kana / {n) fZ 73 9p Channel / () (ij (p) Rrt f (t