SU559381A1 - Integral dynamic element - Google Patents

Description

one

The invention relates to the field of computing and can be used in digital computers and devices.

In modern digital computers, dynamic systems are widely used alongside potential element systems; pulse systems of elements.

The main distinguishing features of dynamic element systems are; the use of pulsed power circuits and the availability of circuits for short-term storage of I1c {) storage.

There are dynamic systems of elements using various methods of temporary storage of information. The most technologically advanced are the dynamic elements of the SEM memory 1111M capacitor and based on regenerative expansion 1. These schemes can be made in the integral performance, -. which is a desirable condition for each system of elements.

However, the known circuits have a large number of supplied clocks, which are complex: clocking pulses, as a rule, are two-polar, which makes it difficult to create clocked impulse generators in an integral design.

For short-term information storage, for example, a trigger with direct connections to multi-emitter transistors is used. However, it does not allow to perform logic functions, moreover, it requires bipolar input pulses.

The purpose of the invention is to ensure the execution of logical functions, AND, OR with short-term information storage.

This is achieved by the fact that in an integrated dynamic element containing a trigger on multiemitter transistors with collector-base connections, each of which is connected by an emitter to the clock bus, the remaining emitters of the transistor of one of the arms are connected to the input signal buses, and the second shoulder contains asymmetry means in the form of active resistance; the asymmetry means are made in the form of resistors included in the emitter-circuit of the transistor, in order to increase reliability, the emitters of the second-shoulder transistor are connected to the paraphase input buses; signals; used as a means of asymmetry of the circuit, the resistor connected to the emitter circuit of the transistor of the second trigger is connected to the common bus; as a means of asymmetry -G, a transistor connected according to a common emitter circuit, the base of which is connected to the collector of the second shoulder of the transistor, is used to obtain an additional inverted output and the possibility of using a single emitter transistor in the second shoulder; As an asymmetry, a diode connected v by one electrode to the collector of the second transistor, the shoulder, and the other electrode to the source of the reference voltage was used to fix the output signal level and use a single emitter transistor in the second shoulder. FIG. 1 shows an integrated dynamic element with output amplified stages on transistors, in which the asymmetry in the shoulders of the flip-flops is introduced with the help of additional resistors included in the input: element circuits; in fig. 2 - integral dynamic element, the 1st of which the forced installation of the trigger in the zero state is realized with the help of the resistor included in em1; the transistor of the transistor, the second arm of the trigger; in fig. Integrated dynamic element with asymmetry introduced into the trigger arms using a voltage source and a fixiaiin diode; in fig. 4, - an integral dynamic element, in which the amplifying cascade on a transistor connected according to the scheme with OE, introduces asymmetry into the trigger shoulders, is shunted by the EB transition, the base of the multiple emitter transistor to the clock voltage bus, and provides the possibility of obtaining an additional inverted output. The operation of all the listed elements is identical due to their execution on the basis of a trigger with direct connections and means of asymmetry in the arms, therefore, we consider only the element shown in FIG. 1. The integral dynamic element contains direct inputs 1, 2 and 3 of the logic element of the logic element, input 4 of the clock voltage, inverse inputs 5, 6 and 7 of the logic element, additional resistors 8, 9 and 10 for imbalance, emitters 11 and 12 connected to the input of the clock voltage, multi-emitter transistors (MET) 13 and 14, covered by cross-trigger connections, resistors 15 and 16 of collector loads, power supply voltage 17, inverse output 18, and direct logic output 19 of the logic element. The device works as follows. In the operation of a dynamic element, two modes can be distinguished; the mode of formation (recording) of the logical function and the mode of temporary storage of the obtained, logical function. The clock voltage is fed to input 4 (to the combined pair of emitters 11 and 12), the information in the direct code is fed to the inputs 1, 2, and 3, and in the inverse to 5, 6 and 7. The installation of a new trigger state occurs when applying a positive clock pulse voltage to the emitters 11 and 12, which are closed. Information arrives at the inputs in the paraphase code. A unit of information is encoded at a high signal level. Suppose that all direct inputs are high. signal levels, then the multi-emitter transistor 13 is closed across all emitters (a high level on the clock bus), and transistor 14 is open, since a low voltage level is applied to the emitters 5, 6 and 7. If all the direct inputs are supplied with a low voltage level, then inputs 5, 6 and 7 are high levels (due to the paraphase input). With such a combination of input signals, the transistor 14 is closed for all emitters and the transistor 13 is open. Let rf direct inputs of the logic element have a low voltage level (where P is i, 2) and, respectively, at t-inverse inputs - low level ( where m3-n with the total number of information dov equal to three). The combined pair of emitters is disconnected from the trigger circuit (high level on the clocking bus). Following up Asymmetry of the trigger shoulders due to resistors 8, 9 and 10 creates an advantage for opening 13 in transistor 13, positive feedback leads to opening of transistor 13 and closing transistor 14. In this case, the output 19 also implements a logical function And for direct inputs element output 18 function. Qi - I-ME for high levels of inverse input signals. Then, according to the de-Morgan rule, output 19 is a function OR NOT, and output 18 is a function -OR for low levels of input signals, i.e. the system of elements has a functional completeness. The output 18 implements a logic function AND for high levels of input signals and inputs 1, 2 and 3. At output 19 a logical function OR is implemented for low levels of input signals on inputs 5, 6 and 7. After the formation of a new state, a clocking voltage is applied, the voltage is O. The combined emitters 11 and 12 are shunted to the ground, fixing a new state. In this case, the remaining emitters of the transistors are disconnected from the trigger circuit. The integral dynamic element depicted in .fig. 2, consists of one multi-emitter transistor (MET 2O, one two-emitter transistor 21; and collector loads 22 and 23.: Its principle of operation is similar to the element shown in Fig. 1. The imbalance is introduced by a resistor 24 connecting one of the emitters of transistor 21 with common bus (ground), 25 - inverse output of the element, 26 - direct output. The emitters of the transistors of both arms of the trigger are connected to the clock voltage bus. In the integrated dynamic element shown in FIG. 3, imbalance is introduced by the source of fixation voltage 2 and diode 28. Ying The tegral dynamic element shown in Fig. 4 consists of a trigger on transistors with collector-base connections and an amplifying stage on transistor 29, which performs the unbalance function and also serves to obtain an additional inverse value of information .

Claims (6)

1. An integrated dynamic element containing a trigger on multiemitter transistors with collector-base signals. Sources of information taken into account during the examination: 1.Filippov A.G. Transistor Di: Dynamic Elements of a Digital Computer. L1 .., Soviet radio, 1969. 2. Electronics, 1967, No. 4, p. 42. These are, each of which is connected by an emitter to the clock pulse bus, which is characterized by the fact that, in order to perform the logical functions AND, OR, the remaining emitters of the transistor of one of the arms are connected to the input signal buses, and | the second arm contains asymmetry means in the form of active resistance. 2. The device according to claim 1, that is, that the asymmetry means are made in the form of resistors included in the emitter circuit of the transistor. 3. The device according to pp. 1 and 2, that is, with the aim. increasing the reliability, the emitters of the transistor of the second arm are connected to the paraphase input signals. 4. The device according to claims 1 and 2, which is based on the fact that the resistor used as a means of asymmetry of the circuit, connected to the emitter circuit of the second trigger transistor, is connected to the common bus. 5. The device according to claim 1, which is based on the fact that a transistor connected according to the scheme with a common emitter, the base of which is connected to the collector of the transistor of the second trigger arm, is used as an asymmetry circuit in order to obtain an additional inverted output and the possibility of using a single emitter transistor in the second shoulder of the trigger. 6. The device according to claim 1, characterized by the fact that a diode connected by one electrode to the trigger collector of the second trigger arm and another electrode to the reference voltage source is used as the asymmetry means, and to fix the output voltage the signal and the possibility of using a single emitter transistor in the second shoulder of the trigger. 18 567 .f 2