SU549827A1 - Device for transmitting and receiving information for distributed objects - Google Patents

Description

which qing is connected to the synchronization input of the coding block 2.

The input of the coding block 2 is connected to one of the inputs of the adder 4 modulo. To the second input of the adder 4 is connected to the output of the additional coding block 5 addresses, the input of which is connected to the additional (serial) output of the generator 6 addresses. The synchronization input of the block of addresses 5 is connected to the additional output of the control unit of the transmitting side. The output of the adder 4 is connected to the first input of the transmitter 7. The parallel inputs of the generator 6 are connected to the outputs of the address register 8, the synchronization input to one of the outputs of the control unit 5, and the output to the second input of the transmitter 7.

On the receiving side, the second output of the receiver 9 is connected to the input of the addressing unit 10, and the first is connected to one of the inputs of the adder // modulo. The second input of the modulo adder is connected to the output of the additionally entered coding block 12 of addresses, the input of which is connected to the output of the block addresspip W. The output of the adder // is connected via coding block 13 to the information output register 14. The other output of the block 13 is connected to the input of the selector 15 in an error, and the output of the selector is connected to the enable input of the register 14. The synchronization inputs of the address coding block 12, block 13, addressing block 10 and register 14 are connected to the corresponding outputs of the receiving side control block 16. Coding unit 12 must be made active on a shift register with feedbacks (generating check characters for any address code combination) or passive (storing only one address code combination along with check characters). ; The device works as follows.

The address of the receiving side (the peripheral point for which the information is intended) is written to the address register 8, and the information itself is written to the information block /.

The address generator 6 generates one of the known methods of address switching signals, which, through the transmitter 7, the communication channel and the receiver 9 and ist}, feed into the inputs of addressing units 10, making a temporary separation of the latter (an alternate address connection occurs).

At the moment of addressing the receiving side (one pz of peripheral points) to which the information is intended, which is recorded on the transmitting side by the coincidence of addresses in register 8 and generator 6, the information on the cycles specified by control unit 3 begins to flow to block 2 and then through adder 4 and transmitter 7 to the channel. In the coding block, verification symbols are generated and added to the information. Simultaneously with the serial output of the generator 6 characters of the address code

the combinations arrive at the additional coding block 5 of the addresses where the verification symbols are generated and added to the combination, and then to the second input of the adder 4. In the adder, modulo symbols are added to the information code combination with the address and verification symbols of the address code combination. At the receiving side

information from the output of the receiver 9 is fed to one of the inputs of the adder //, the second input of which receives from block 12 characters of the address code kmbination corresponding to the address of this peripheral point,

together with verification characters. The symbols received from the channel are summed modulo the output symbols of block 12 and arrive at block 13. If the address of a point produced by generator 6 on the transmitting side coincides with the address of this point of the receiving side (at the output of addressing block 10) and the channel did not fail then, from the output of block 13 to the selector of 15 errors, the zero syndrome enters and the selector generates a signal “correctly, allowing reading of the received information from the register 14. Otherwise (there is no correspondence of the addresses, errors in the channel, or both dnovremenno) encoder generates a non-zero syndrome ( "error), and a selector suppresses the received information.

In more detail MOJKHO devices to consider on a private example. Let, for example, the device works with step by step

synchronization when the signals are an address connection. . . i -3, i-2, i-1, ... (see FIG. 2) image) sweat is a recurrent M-sequence, and the current value of the address of the receiving point point associated with the transmitting

side, determined by the phase of the M-sequence.

Thus, on the basis of the address switching signals, the blocks of 10 all points of the receiving side (in our example, their

16, a small number of points are taken up to simplify the time diagram. The "track of the current value of the address with which the transmitting side is currently associated.

Since the signals are addressable. . . i-4, i-3, i-2, i-1, i. . . (shown in Fig. 2 are shaded) have a small volume (in the example given, 1 bit), as indicated, errors are possible.

To reduce the likelihood of an error in the proposed device, the redundant coded address is additionally applied to the information without being destroyed by the latter, as shown in the timing diagram. After transmitting the switch signal to i-4, the address information 1001 (in the decimal code number 9) from the output of the information block / enters - in block 2, where the check symbols 011 are generated. At the same time, the address / -4 in the binary code 1110 (the decimal number 7 a) from the output of the address generator 6 is fed to the code 5 address block, where the check characters 010 are generated. The information encoded by the redundant code from the output 2 and the address from the output 5 are fed to the adder 4, the output of which produces a bit of the sum of code combinations modulo two 0010111, to ora is transmitted through a radio channel is allocated a receiver 9 and applied to one input of the adder P. The other input of the adder and postzpaet output from block 12 the encoded redundant codes t-4 address generated addressing block 10 points of the receiving side. Since the code combinations from the outputs of blocks 5 and 12 with the correct address are exactly the same, as a result of modulo two summing up in block 11 of the codes from the outputs of block 12 and receiver 9, the information code is restored. The recovered information code at the output of block 11 in this case exactly coincides with the original code combination at the output of block 2, therefore, information block 13 produces a zero syndrome indicating that there are no errors.

For I-3 addresses in the timing diagram, the case of errors in the address and information is shown. As a result of the distortion of the i-3 signal of the address connection on the i-side of the signal, the C-th address was falsely allocated, which led to a mismatch of the combinations at outputs 5 and 12. As a result of the distortion in the channel of the 5th bit of the information signal, the correspondence between the outputs was broken. 4 and out. 9. In the end, recovering the code combination on the out. Y / does not coincide with the initial one at output 2 (non-coincident bits are marked with exclamation marks), as a result of which information block 13 produces a non-zero syndrome indicating that an error has been detected. The case of an error only in the address is illustrated on the i-2 address. There is no correspondence between the outputs of the coding blocks of 5 and 72 addresses. If the error is present only in the information signal

(d-1 address), the correspondence between the outputs of blocks 4 and 9 is broken.

Claims (1)

Invention Formula A device for transmitting and receiving information for distributed objects, containing on the transmitting side an information block whose output is connected to the first input of the modulator through the coding block, the outputs of the address register are connected to the corresponding inputs of the address generator whose output is connected to the first input of the transmitter, the clock inputs of the information block, address generator and coding block are connected respectively to the output of data bits of the bits, the output of cycles of the address bits and the output of the coding cycles of the control unit, and at the receiving side - the receiver, the outputs of which are connected to the input of the addressing unit and one of the inputs of the modulo adder, the output of the modulo adder is connected to the output register via a decoding unit; the second output of the decoding unit is connected to the error selector, and the output of the latter is connected to the enable input of the output register; The synchronization inputs of the decoding unit, the output register and the addressing unit are connected to the corresponding outputs of the control unit, characterized in that, in order to increase the noise immunity, the address-coding unit is inserted into the device on the transmitting side, the input is connected to the additional output of the address generator, the synchronizing input is to the additional output of the control unit, the output to the second input of the adder, the output of which is connected to the second input of the transmitter, and on the receiving side a coded block is entered and addresses, the input of which is connected to an additional output of the addressing unit, the output - to the second input modulo su.mmatora tso, and a clock input connected to the output control unit donolnitelnym. POGOT / MRTLL channel fJpaS transmission Error SUHipop. OiuuSKaSsSpece i-2 1-3 Lfig. 2 And g / | g | / N And t% j Oshadka ffadrese Prae. transmission and information