SU534867A1 - Level distributor - Google Patents

Description

(54) LEVEL DISTRIBUTOR

The invention relates to digital computing technology, can be used in the design of cost-effective multi-f "analog level distributors on integrated circuits. . . Known multichannel distribute | whether levels on shift registers 1. In addition, well-known distributors of levels ya 2 Jt channels (P is an even number), containing registers, the outputs of which are connected to the output tires G2, Known devices are unreliable. The purpose of the invention is to increase the reliability of the distributor - it is achieved by the fact that a four-stage is entered into the level distributor by 2 P / channels (/ Tl is an even number) containing registers whose outputs are connected to the next ones. the counting trigger, the first and TpeTi e of which are under: are included: to the answer yuTSym temtovym Bxo-j give the first register, and the second and fourth | to the corresponding clock inputs of the second, and the first output of the first register is connected to the input of the second zero, and the last the output of the second is at the entrance of the mouth. " first zero. The drawing shows a block diagram of the distributor | Level limiter. i Assume that in the initial state rpitrirep 1 has on its arm 2 a unit code, on terminals 3-5 there is a zero code, and registers 6 and | 7 are in zero state, I. Then the high level unit acts; | Vuet only at input 8, at output 9 of register b there is a working signal, and I input the device impulse from an external generator and the accelerator 4 starts trigger 1 to state one. The 1st pitch unit now acts only on INPUTS 11 and 10, and an input signal appears at input 12 of register J7. The second pulse arriving at the flO lasess again switches trigger 1, causing Tate to appear at output 13 of register 6. ii The third pulse at input 10 switches trigger 1 to state 1 at the PL. 1h 5, which leads to the inclusion of the register l | 7j of its output 14. The next impulse at input 10 returns uaer trigger 1 to the initial state. After the switching of the neck, distribute the hfl levels in the same way as o6pa3Oi | i. It can be seen that the clocking I, inputs to each of the registers 6, 7 are barreled signals (level one). They are received at time intervals corresponding to the duration of the working signal on the playlist. input 15 of register 7, on pLeche 41 of input I 16 of register 6, on arm 5 of input 111 of register 7. Thus, the switching signals to each of the two registers do not follow each other, but through temporary breaks. This dramatically increases the reliability of the level distributor compared to the known ones.

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Claims (2)

PT f, Formula of the invention The level distributor for 2 If KaofoioB (I is an even number), containing registers, the outputs of which are connected to output tires, characterized in that, in order to increase its reliability, enter the four-stable counting triggers, first and the third shoulder is connected to the corresponding clock inputs on the first pattern, and the second and fourth clock inputs of the second,; when the first output of the first register is connected to the second zero input, and the last output of the second is input yqth zero of the first. Sources of information, taken in the exhibition at the examination :; "1. Author's certificate of the SSS | № 439920, class H 03 K 17/62, 02.01.73. 2.I. N. Bukreev and others. Microelectronic circuits of digital devices,;. IM ,, / Sovetskoye Radio, 1973, cip. 231, rsh.6.25.