SU507926A1 - Digital thyristor converter control device - Google Patents

Description

The proposed device consists of oscillating pulses 1, generating two sequences of unipolar pulses of clock frequencies F. and F, which are shifted between each other in time at equal intervals; launching circuit 2, which detects the launch of the device at the moment of arrival of the first pulse from the output of the null organ; Correction circuit 3 angle control and zero converter installation; two synchronization schemes 4 and 5, stitching the device from failures and loss of information; subtraction circuit 6; counter 7. null organ 8; schemes are sewn 9; voltage converter - frequency 1O; control pulse distribution and generation circuits 11, which distributes the overflow pulses of counter 7 along the two control channels and generates the powerful pulses necessary to open the thyristor. The digital thyristor converter control device operates as follows. In the mode when there are no setpoint frequency pulses and feedback frequency pulses when the alternating network voltage across the zero voltage passes through the zero value, the zero organ 8 produces a clock pulse, under which a trigger 2 is triggered and allows the clock pulse frequency p to pass The input circuit of subtraction 6 and further to the input of the counter. The filling time Tj of the counter 7 and the frequency of the mains supply are as follows: - Cmu Ezotodar initial installation trigger high bit of the counter 7 in the single state, output impulses lsy overflow counter 7 are shifted in vryumeni off half a repetition period to emasculate "ul-body 8. (Ts-7 in FIG. 2). Consequently, the phase of the pulses of the aft counter of 7 relative to the output pulses of the zero organ (UQ in Fig. 2) corresponds to the steering angle -oSb9OO. . 2), which generates control pulses with the necessary pair

meters.

The operation of the circuit in the presence of frequency pulses set f and frequency pulses feedback f occurs as follows.

Claims (2)

It goes half the capacity of the counter 7. As a result, the phase of the output pulse can change to (phase reversal), which will lead to emergency mode. Upon receipt of the frequency of the task. to the input of the synchronization circuit 4, the latter stores them and then enters synchronously with the clock frequency f to the second counting input of the counter 7. This achieves protection of the circuit against failures and loss of information. Consequently, in addition to the clock frequency F., the counter 7 is filled with the frequency pulses of the reference f, which leads to a decrease in the counter filling time, 7, i.e., the control angle cL decreases (and, - fig 2), which in turn causes voltage at the output of the thyristor, converter. This voltage, acting on the control object, causes its functioning. At the same time, the code voltage of the thyristor converter is fed to the voltage converter -frequency -10. The feedback frequency pulses f through synchronization circuit 5 synchronously with the clock pulses p are fed to subtraction circuit 6, which provides a continuous difference between the number of feedback frequency pulses. Consequently, in this mode, the counter 7, besides the setpoint frequency f J, is filled with a frequency difference, () is equivalent to applying the clock frequency F and the difference of the setpoint frequency f, and the feedback frequency to the counter. СОР, which leads to an increase in the filling time of the counter, i.e., to an increase in the number of directions with. When equality f fj is reached, the transition process ends, that is, in the account. Match 7 records and subtracts the same number of pulses. In the steady state, the control angle is determined by the number of impulses: ow N, recorded in counter 7 until the frequencies f J and f gj are equal. . The use of a circuit for subtracting 6 pulses of frequency fpjj from a clock frequency P allows one to increase the speed of the circuit, especially when working with low reference frequencies, and also to apply counter 7, which greatly simplifies the circuit. In the course of operation, a mode of large or long mismatch in the control system is possible, i.e. The difference between the number of setpoint and feedback pulses per unit time is exceeded. To prevent this, a protection circuit 9 is used, which contains an analog pulse delay circuit, a zero-body 8 by values corresponding to the maximum Lj and the minimum O-ji jiu. permissible control angles, and an immediate protection circuit that operates as follows. When you change the angle of control within the l. . "F" schemes g VIH - - GDAKS. the protection passes the overflow pulses of the counter into the distribution circuit and the formation of control pulses 11. When the overflow pulses leave the specified interval, the protection circuit 9 blocks the output of counter 7, simultaneously emitting pulses of CI or (L. depending on the mismatch sign) to until the pulse of the overflow of the counter 7 again enters the specified interval. When the converter operates on a load with a different nature of total resistance, the control angle ci, at which the output voltage of the converter Zero can have different values. For setting this angle (if it is not equal to 90 °), a correction circuit of 3 steering angles serves and setting a zero converter which supplied a burst of pulses corresponding to the required change of the steering angle to the control unit. - neither the control angle L - the pulse packet synchronously with F, goes to the counting input of the counter 7, to increase - synchronously with FJ to the subtraction circuit 6. When the converter is working on the active load, the angle dQ - 18О ° is set by removing the record one The probes are in the highest bit of the counter 7. Similarly, the control angle is corrected during operation. 5 6. 6 claims 1. A digital thyristor converter control device comprising a clock pulse generator, connected via a trigger circuit to a counter input, the output of which is connected to a thyristor control electrode, is a null organ connected to the trigger circuit, which is that, in order to improve the control accuracy and to provide for autonomous operation, a voltage-frequency converter, two synchronization circuits, an extractor circuit, the first output of the trigger circuit is connected to one from the inputs of the first synchronization circuit1 1 directly and with the first input of the counter through the subtraction circuit, the second output of the startup circuit is connected to the second input of the counter via the second synchronization circuit, and the output of the voltage-frequency converter is connected to the second input of the first synchronization circuit, the output of which is connected to the second input of the subtraction circuit. 2. The device according to claim 1, wherein, in order to provide installation and correction of the control angle and protect the device from phase reversal, the device contains a correction circuit and control angle settings, the inputs of which are connected to clock outputs, and the first and second outputs, respectively, with the third input of the counter and the third input of the subtraction circuit, and the protection circuit, two inputs of which are connected respectively to the zero-body output and the output of the counter, and outputs via the distribution circuit and the imp lsov connected to the control exercise SHL yushim electrode of the thyristor. 9g1 / f o FIG. g