SU506890A1

SU506890A1 - Functional angle converter to digital code

Info

Publication number: SU506890A1
Application number: SU2056040A
Authority: SU
Inventors: Вадим Викторович Меер; Лев Владимирович Былинский
Original assignee: Особое Конструкторское Бюро Вычислительной Техники Рязанского Радиотехнического Интитута
Priority date: 1974-08-26
Filing date: 1974-08-26
Publication date: 1976-03-15

Description

1one

Насто щее изобретение относитс к области вычислительной техники и может быть использовано в электромеханических счетнорешающих устройствах и навигационной технике .The present invention relates to the field of computer technology and can be used in electromechanical computing devices and navigation technology.

Известен функциональный (синусно-косинусный ) преобразователь угла поворота в цифровой код, содержащий синусно-косинусный вращающийс трансформатор (СКВТ), включенный как фазовращатель и соединенный с согласующими блоками, выполненными в виде преобразователей «фаза-число имнульсов , цифровые интеграторы, выход каждого из которых подключен к первому входу другого интегратора, к вторым входам интеграторов подключен генератор импульсов, а также источник опорного напр жени и дешифратор нул . При выделении с помощью согласующих блоков определенного числа импульсов генератора на регистровых выходах цифровых интеграторов вырабатываютс коды синуса и косинуса угла поворота ротора СКВТ.A functional (sine-cosine) angle-of-turn converter into a digital code is known, containing a sine-cosine rotating transformer (SCRT), included as a phase shifter and connected to matching units made in the form of phase-number impulse converters, digital integrators, each output connected to the first input of another integrator; a pulse generator is connected to the second inputs of the integrator, as well as a source of reference voltage and a decoder zero. When using a matching block of a certain number of generator pulses, the sine and cosine codes of the rotor of the SCRT are generated at the register outputs of the digital integrators.

Наиболее существенным недостатком известных устройств вл етс наличие погрещности , обусловленной нестабильностью амплитуды и фазы напр жений СКВТ вследствие изменени его коэффициента трансформации под действием температуры окружающей среды , уходов частоты и амплитуды сетевого питани . Кроме того, возможно возникновение погрегпности при нестабильности частоты генератора управл ющих импульсов. Дл повышепи помехоустойчивости в предлагаемой функциональный преобразователь введены декодирующий преобразователь, аналоговый сумматор и запоминающее устройство . Опорные входы согласующих блоков подключены к выходу сумматора. РегистровыйThe most significant drawback of the known devices is the presence of the mismatch caused by the instability of the amplitude and phase of the ACS voltages due to a change in its transformation ratio under the influence of the ambient temperature, frequency drift and amplitude of the mains supply. In addition, the occurrence of pogragpnosti is possible when the frequency of the generator of control pulses is unstable. To improve noise immunity, a decoding converter, an analog adder and a memory device are introduced into the proposed functional converter. The reference inputs of matching blocks are connected to the output of the adder. Register

выход одного интегратора подключен к дешифратору нул , а другого - через последовательно соединенные шифратор приращени кода и запо.минающее устройство к входу декодирующего преобразовател , выход которого соединен с одним из входов сумматора, другой вход которого подключен к источнику опорного нанр жени . Дешифратор нул подключен к генератору импульсов и к шифратору приращени кода, а третьи входы интеграторов соединены с выходами согласующих блоков.the output of one integrator is connected to the zero decoder, and the other through serially connected code increment encoders and a storage device to the input of the decoding converter, the output of which is connected to one of the inputs of the adder, the other input of which is connected to the reference source. The zero decoder is connected to the pulse generator and the code increment encoder, and the third integrator inputs are connected to the outputs of matching blocks.

На чертеже представлена блок-схема описываемого преобразовател , содержащего СКВТ 1, соединенный с согласующими блоками 2, 3, два цифровых интегратора 4, 5, выход каждого из которых подключен к первому входу другого интегратора, а ко вторым входам интеграторов подключен генератор импульсов 6. Третьи входы интеграторов 7, 8 -The drawing shows the block diagram of the described Converter containing SCWT 1 connected to matching blocks 2, 3, two digital integrators 4, 5, the output of each of which is connected to the first input of the other integrator, and the second inputs of the integrators connected pulse generator 6. Third integrator inputs 7, 8 -

Claims

The inputs for setting initial conditions are connected respectively to the outputs of matching blocks 9, 10. Various types of analog-to-digital converters can be used as matching blocks, the output code of which corresponds to the ratio of the amplitude of the alternating voltage to the reference voltage, for example, operating according to the principle of comparison. and subtraction or two-step integration. The reference inputs 11, 12 of the matching blocks are connected to the output of the analog adder 13, to the inputs of which are connected the source 14 of the reference voltage and the decoding converter 15. The register output 16 of the digital integrator 5 via the serially connected increment encoder 17 and the memory 18 is connected to the decoding converter 15 The register output 19 of the digital integrator 4 through the decoder zero 20 is connected to the gate input 21 of the pulse generator 6 and to the gate input 22 of the encoder 17. The device operates t as follows. Taking into account the voltage instabilities of the ACS powering frequency and amplitude and temperature-frequency instability of its transformation ratio, the voltage amplitudes of the quadrature windings Us and (/ s at the angular position of the rotor y can be represented as U, (± b) smr. T /, (l ± ycos-r, where Urn is the nominal value of the amplitude of the supply voltage of a SCRT; K is the nominal value of the ratio of the transformation of the SCRT in the absence of destabilizing factors; Oj is the total relative error of the amplitude caused by the action of destabilizing factors. Matching blocks 2, 3 produce, respectively, the digital codes NS and, equal to the ratio d; /. m - and, L., - t - - - TG where / o is the output voltage of the analog adder 13. From outputs 9, 10 blocks NS codes and enter the inputs for setting the initial conditions (7, 8) of digital integrators 4, 5. The output of each of digital integrators 4, 5 is connected to the input of another integrator, so that when the clock integrators arrive at the second inputs of the integrators 6 equation of the form y + with initial conditions y (Q) ,, / (0) / V ,. When fixed at the register output 19 of the digital integrator 4-zero code, the decipheror zero 20 outputs a signal to the gate inputs 21 li 22 of the generator 6 and the encoder 7, respectively. At the entrance 21, the generator 6 is blocked and the impulses are prevented from entering the digital integrators, and at the input 22 the encoder 17 is permitted. At this moment, the module code N. ---. YNI + NI differs according to expressions (1) and (2) from its nominal value by the increment value corresponding to the sum of 8. hydrochloric pogreschnosti. The code increment encoder 17 extracts the code equivalent of the error AjV and outputs it with a sign to the memory 18. The decoding converter 15 associated with the output of memory 18 generates the correction voltage At / proportional to the value of the input code, which is fed to the analog adder 13 The output voltage of the analog adder 13 is and, and, ± sh and, (± sh) where Ui4 is the voltage of the reference source 14 goes to the reference inputs 11, 12 of matching blocks 2, 3 and with equal dU to the error value b fully compensated This is the influence of the latter. When combining in the memory device 18 the function of summation of the increment codes of the DL computed relative to the conventional digital support and the function of storing the value of this sum can reduce the stability requirements of the source 14 of the reference voltage decoding converter 15 and the analog adder 3. This is possible due to the fact that Subsequent cycles of the functional converter automatically select UQ before adjusting the values of b, dU. The accuracy of the compensation is determined by the resolution of the decoding converter 15, the width of which is chosen based on the maximum possible total error when generating the siny and cozy function codes. Thus, when the functional converter is operating, the equality b, is automatically maintained from the outputs 9 and 10 of matching blocks 2, 3 the digital codes sinY and COZY are received, the values of which do not depend on the considered instabilities of the SCRT and its power supply. Claim of the invention Functional angle converter into a digital code containing a sine-transformer, 5 kosknusny rotating connected to matching blocks, integrators the output of each of which is connected to the first input of another integrator, a pulse generator is connected to the second inputs of the integrators, the source of the reference voltage-10 nor the decoder zero , characterized in that in order to improve noise immunity, a decoding converter, an adder, a memory device, and reference inputs co Auxiliary glare is connected to the output of the adder, the register outputs of the integrators are connected respectively to the zero decoder and through serially connected code increment encoder and storage device to the input of the decoding converter, the output of which is connected to one of the inputs of the adder, the other input is connected to the source of the reference voltage, the decoder the zero is connected to the pulse generator and to the code increment emitter, and the third integrator inputs are connected to the outputs of the matching units.

Vn T 1 40