SU481129A1 - Digital phase detector - Google Patents

Description

On srig. 1 shows the structural scheme of the proposed detector; in fig. 2 - timing diagrams explaining the principle of its operation. The digital phase detector contains a dip switch 1, filters 2 and 3, amplifiers 4 and 5, null organs 6 and 7, control unit 8, cycle counter 9, electronic switch 10, pulse generator II, reversible phase counter 12, AND 13 circuit. , zpaka trigger 14, transfer schemes 15 and 16, OR 17 circuit, phase 18 register, code-converter converter 19, digital phase indicator 20, containing the circuit OR 21, triggers 22 and 23, and three And 24, 25 schemes, 26, the circuit “OR 27, the electronic key 28, the adder 29, the trigger of the reverse 30 and the rewind circuit 31. The proposed detector works as follows at once. If the instantaneous phase values do not exceed 2, then at the initial moment the two-pointed switch 1 is in one of the following states, for example, corresponding to the measurement mode, when both signals MI () and "2" are supplied to the detector input (0) The first of these signals passes through filter 2, amplifier 4 and receives pa ilorgi 6. The second signal goes through filter 3, amplifier 5 and enters pa ilorgi 7. The output pulses of the pul-orgap 6 and 7 go through the control unit 8,; i 1 and the input pulses) 1-or-6 besides - on the counter of cycles S. If a signal null-organ 6 take ouopiibiM. then the control unit B on this site opens the electric key 10 and the standard model often 1 1 from the heater P passes the counter phase 12. The control unit 8 closes the signal 10 from the signal of the organ 7 and removes the pulse from the generator 11 n ;; counter 12. So the circuit works in Teneime /, c1I {fishing, and /; selected nz conditional where n is the frequency multiplicity w p of the main harmonic 1 of the modulating signal; t is a solid tel number, chosen depending on the sigral composition of interferences, and is present in them at the input sigals. If the volume: V counter phase 12 choose rabbi L 77.; A. 360 ° (; j. Is the number of pulses per T), then by the time of the initial measurement cycle n, it will be fixed iv, - L - f N ... where L is the code, which is the constant component of fg .. - code, which is proportional to the phase uOi-rotary Af, caused by the non-septic characteristics of the characteristics of filters, amplifiers and il-orgs. After that, at the output of the pickup counter 9, an immo- bial iperalid appears, which enters the control unit 8, and the latter in turn switches the switch 1 to the correction mode, when pa fy 2 and 3 iostot the same signal tii (t, and sets the phase 12 count to 1chip mode. The next cycles of the circuit work in the same way, and the number of impulses received in the phase 12 matcher is Ld.,. The number of BGTs, submits to subtract 12, and, as a result, there will be a number of emuls L. “. If it turns out that; V, 5 180 °, the signal at the output The “P 13” circuit is not formed and the trigger of sign 14 remains in the D initial state of rn1. If it turns out that n -.- 180 °, the output of the “AND 13” circuit generates a signal, it has a trigger and a trigger. Depending on the state sign 14 trigger to work, either transfer 15, connected to one output of phase 12 trigger, or transfer 16, and connected to outputs of phase counter of phase 12. On access control of transfer circuit 15 and 16 from the output of cycle counter 9 of the signal corresponding to the end correction cycle, ir. my or pre-polyple the code from the phase counter, 1 12 through transfer schemes 15 nln 16 and spin-offs from 2) 0 (ro i80- or) and the “ILR1 17” scheme is entered on the phase 18 register. To the register of the phase 18, the forgroup key and ;; ppnepne, proiorpio .chalie code. and, consequently, the phase shift -ij, and converts the code – code as shown in 19. Sign; c hp) voltage code – n converter ;; bind 19 determine the trigger 14. If during the JHICIOT measurement process, place the spot. the instantaneous values of the phase are at a glance of 2. 2. then the phase phase display starts; 1tel 20. The determining number of such npeinJnicinni, to the cooTBeTCTiinn with which; I ;; a phase meter 12 is entered correspondingly to such a text {a nonran; a. Pa vaMennoii Dnagrlps {sd ;. fpg 2) state-owned weekend imiulsa and l-ortio | G and 7 Itz, LJ-2i. The pymuls from the output of the null-orgap 5 p 7 is fed through the scheme "PCR 2; And the counting input of the trigger 22 and on separate trnger 23. When and subsequently 1: ateliol received two g impulses. e pyhoho od one (; the fifth; to the il organ. nj-npiniep without ji 6; l from the outlet of the il-organ 6, or IJoa-i) and b-H; from the output of the bullet-organ 7, the second of these pulses (in the case of L., and Lj /), trigger m. 23 is not perceived. The initial state of the thrusters 22 and 23 is chosen such that the “And 24 posi-tion scheme all but the same third-party signals on its output have a smigm, and on the“ And 25 and 26 ”I enter: wg: 3 but at the level signals on their outputs silgals are absent. In the freeze mode from the BK / YUSHPI phase detector, there are two possible operations of the numbered phase patterns 20. In the first mode, the device works when the first lp-1 repeats the emulsions from the outer code of the first} 6 or-gap 6. Then With the pulse id 6i4, a signal appears at the output of the circuit “And 25” and with some delay, with the arrival of a pulse — the signal at the output of the circuit “And 26. The advancing signal of the circuit“ And 25, first, through the circuit “OR 27 closes the key 28 and prohibits the signal interruption of the ' 26 circuit to the adder 29, and secondly, is written to the adder 29 to be summed s. Subsequently, with the arrival of each pulse from among t / is, ..., f / i; at the output of the circuit "And 25, a signal is formed, fixed by the adder 29. With the arrival of the pulse Uzi, the coordinated triggers 22 and 23 are violated, and the signals at the output of the circuit" And 25 are not generated. The number of pulses recorded in the adder 29, is equal to /. For the case under consideration, t i is 3. In the other mode, phase indicator 20 operates when the pulses from the zero-organ 7 appear first. I.e. when the measurements begin in a short distance between the pulses f / is and Un. In this case, the number of erroneous measurements is / n - /, where / is the number of samples measured, which passed until the appearance of the impulse Uzi; I is the number of measurement cycles passed after the appearance of a pulse Uzi. In this mode, the signal appears at the output of the AND 26 circuit at the moment when the pulse f / 2 arrives; - This signal, through the open source key 28, enters the number n in the adder 29 and sets it by means of the reverse trigger 30 to subtract. By the same pulse by means of the scheme "OR 27, the electronic key 28 is closed. The pulses generated after that at the output of the circuit "AND 25 at the moments of arrival from the zero-organ 6 pulses la-M), ..., C / 1L are written to the adder 29 in the subtraction. After completing n measurement cycles, the number / n - Г will be written in the adder, according to which the correction / -360 ° should be entered into the phase 12 counter. The correction is entered using the transfer circuit 31, which connects bitwise the adder 29 with the phase counter 12. Moreover, the input of the readings / adder 29 into the counter 12 is carried out with a shift of 360 This input is performed according to the signal from the cycle counter 9 to the pulse inputs of the circuits transfer 31. To return to the initial state, the adder 29 and the key 28 are served by an AND 24 circuit, the output of which is formed when the phase shifts are correctly measured. This signal sets adder 29 to

summation and electronic key 28 to the open state.

Subject invention

Digital phase detector containing two-position switch, two filters, two amplifiers, two zero-organs, control unit, cycle counter, electronic key, pulse generator, reversible

a phase counter, the two-way switch inputs are connected to the input sources, and its output is through the first filter, the first amplifier and the first null organ is connected to the control unit, the input of the second filter is connected to the first input source, and its output the zero-organ is connected to the control unit, the first output of which is connected to a two-position switch,

and the second through an electronic key, the second input of which is connected to the output of the pulse generator, to the first input of the reversible phase counter, the second input of which is connected to the third output of the control unit, characterized in that, in order to expand the functionality of the detector, a converter is introduced into it code-voltage, phase register, first OR circuit, two transfer schemes, first circuit

"And, a sign trigger, a second OR circuit, a second electronic key, an adder, a reverse trigger, a third transfer circuit, and a digital phase indicator consisting of a third OR circuit, two triggers, and three AND,

Nrice: 1 inputs of the third OR circuit and the nerve trigger are connected to the outputs of null organs, and the output of the third OR circuit is connected to the second trigger, the outputs of which are connected to the first inputs of the three AND circuits

the second inputs of which are connected to the output of the first trigger; converter input code voltage through phase register, first OR circuit, first transfer circuit, one input of which is connected to the output of the counter

cycles, sign trigger, the second output of which is connected to the second transfer scheme, and the first AND circuit is connected to the first output of the reversible phase counter, the second output of which through the second transfer scheme is connected to the first OR circuit, the third input of the reversible phase counter through the third transfer circuit , an adder, a reverse trigger and a second electronic key are connected to the “AND digital phase indicator circuit.

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