SU467352A1 - Device to control message format - Google Patents

Description

The device for controlling the message format contains a counter 1, a valve 2, a register 3, a control unit 4, a storage unit 5, a decryptor 6, scaling circuits 7 and 8, AND 9-12, OR 13 and trigger 14 circuits. The device operates as follows . Depending on the program entered from the sensor of program 15, which is transmitted via buffer register 3 to control unit 4, the device can either directly send character data from sensor 16 to register 3 directly to information receivers 17 to register (transmit) these data, or pre-record incoming data in the storage unit 5 with simultaneous control of the format (number of characters) in the generated message, and then send the data from the storage unit 5 to the receivers inf rmatsii 17. In the case of mismatch of characters written in the storage unit 6 messages with a predetermined program using the message number of characters, transmission of data in the data receiver 17 can be locked. In the control mode of the message format, a special service symbol is placed at the beginning of the program, which means that the character following it is the length of the generated message, represented in binary code. The operation of the circuit in the control mode of the message format is as follows. In the initial state, trigger 14, counter 1, scaling circuits 7 and 8, and storage unit 5 are reset to zero (zero) by a signal from control unit 4. When starting the message generation program, the device polls the program sensor 15. When polling the register input 3, the device receives the code of the first service symbol, which is a sign of the operation mode of the device with control of the message format. Simultaneously, the register 3 receives a signal from the control unit 4, which allows recording information from the sensor of program 15 .. The deflator 6, connected to the output buses of the register 3, decrypts the code of this first service symbol and generates a signal that goes to the first input of the scaling circuit 7. This the same signal through the circuit "And 12, to the second input of which a synchronizing signal is fed from the control unit 4, is fed to the input of the installation in a single state of the trigger 14. When it arrives from the control unit 4 to the second input of the scaling circuit 7 The resolving signal produces a signal that is fed to the input of the OR 13 circuit and to the input of the AND P circuit. The output signal of the circuit 13 is input to the decryption decoder 6 input. The next interrogation of the program sensor 15, the binary format code (the number of message characters ). At the second input of the circuit "AND 11, the synchronizing signal from the control unit 4 comes. The output signal of the circuit" 11 goes to gate 2 and enables the coding of the format code from register 3 through the gate to counter 1. Then the signal goes to the input of circuit 7 from control unit 4, and returns it to its original state. After this, the polling signals from the control unit 4 transmit data from the information sensors 16 symbolically, first into register 3, then (via a signal from the control unit 4) to storage unit 5. The order of polling information sensors 16 is determined by the input from the sensor the program. When writing each character of the message being formed into the storage unit 5, the control unit 4 generates a counting pulse, which is fed to the input of the AND 10 circuit, the output signal of which is fed to the counting input of counter 1. When replacing a character mistakenly entered by the operator, to the input of the decoder 6 during polling one of the sensors of information 16 receives the service character code Replacement, which eliminates the preceding character in the subsequent processing of the message in the computer and replaces it with the character following it. When the "Replace the output signal of the decoder 6" symbol is received, it enters the input of the scaling circuit 8 and when it receives the resolution signal from the control unit 4 sets it in one state, thereby prohibiting the passage of counting pulses produced by control units 4 to the counting input of counter 1 through the circuit "AND 10. The scaling circuit 8 is reset to the initial state after writing two symbols into the storage unit 5 (the service symbol" Replacement and the symbol following it). When a service character enters register 3, the end of the message (the last character of the message being formed), the output of the decoder 6 generates a signal that arrives at one of the inputs of the AND 9 circuit. The second input of this circuit receives a signal from the single output of the trigger 14, the third input the signal from the output of the counter 1. If the binary number recorded at the beginning of work in counter I (this number represents the number of characters in the binary code in the message) coincides with the number of characters recorded in the operational storage unit 5, the output of the counter a zero signal appears. Due to this, the signal at the output of the circuit "And 9 is not generated, and the control unit 4 generates control signals which are fed to the inputs of the storage unit 5, register 3 and information receivers 17. These signals are used to transmit character-by-character data from the storage unit 5 to the information receivers 17

If the number of characters recorded in memory 5 in block 5 does not match the binary number recorded in counter 1 at the beginning of operation, a single signal is generated at the output of the counter. Thus, if there are AND 9 signals at the inputs of the single output of the trigger 14, output of the decoder 6 (when the End message character arrives) and output of the counter 1, the output of the AND 9 circuit produces a single signal that goes to the control unit 4 and blocks further operation of the device. As a result, data is not transferred from storage unit 5 to information receivers 17.

Subject invention

A device for controlling the message format, comprising a counter, a valve and a register whose input groups are connected to input groups of the device, characterized in that, in order to increase the reliability of the information, it contains a storage unit, a control unit, a decoder, scaling circuits, and schemes, the OR circuit, a trigger, wherein the first group of outputs of the register is connected to the group of outputs of the storage unit, the groups of inputs of the decoder, the valve, the control unit and the groups of outputs of the device, the corresponding outputs of which are connected trigger outputs of the control unit, the inputs of which are connected to the first output of the decoder and the output of the first circuit "And whose inputs are connected to the outputs of the counter, trigger and the second output of the decoder, the third output of which is connected to the signal input of the first conversion circuit, the output of which is connected to the first input of the second “And the output of which is connected to the subtractive input of the counter, the installation input of which and the installation inputs of the storage unit, the counting circuits and the trigger are connected to the installation output of the control unit tim corresponding outputs are connected to inputs razretayuschimi counting circuits, the second input of the second circuit "And, the first inputs of the third and fourth circuits" And, with the storage unit, and inputs to the first input circuit "OR, the second input of which is connected

with the output of the second scaling circuit and the second input of the third circuit "And, the output of which is connected to the control input of the valve, the outputs of which are connected to the inputs of the counter, the fourth output of the decoder is connected to

the signal input of the second scaling circuit and the second input of the fourth AND circuit, the output of which is connected to the single trigger input, the output of the OR circuit is connected to the inhibitor input of the decipher, and the group

the inputs of the storage unit connected to the second group of outputs of the register.