SU428373A1 - THE GENERATOR OF THE FAULTY SEXUALLY SEQUENCE OF PULSES - Google Patents

Description

The proposed device relates to the field of generating discrete functions and, in particular, to pseudo-random sequence generators and Mpulsov, and can be used to simulate a straight course line or glide path of aircraft landing systems, as well as in computing devices for technical development and coding devices. A device consisting of a shift register is known, the unit outputs of the latter and i-ioro bits of which are modulo-two connected to cyiMiMaTOpa, and the unit outputs of the n-th digit of the shift register are connected to the inputs of the shaping unit. A pedostat of a known device is the low stability of ps & generation in the event of a sequence due to constant wiring between the element of the feedback circuit and the bits of the shift register, as well as due to the pulses of the shift register triggering the previous bits Dov shift register. The aim of the invention is to increase the stability of the generator. The goal is achieved by the fact that the generator contains decoupling elements and a matching unit consisting of a series-connected differentiation element and a delay element. In this case, the inputs of all the bits of the shift register are connected via disconnecting elements to the common generator, and the output of the modulo-two adder is connected to the B1 INPUT of the first armature of the shift register via the matching unit. The modulo-two summator contains two AND circuits, the outputs of which through the corresponding | Differential differentiation elements are connected to the inputs of the OR circuit, the output of which is connected to the output of the cyauiaTora. The first inputs of the AND circuits are connected respectively to the first and second inputs of the Mmator sous modulo two, the third input of which P1 is connected to the second inputs of the circuits And, to the first directly, to the second through an inverter. The drawing shows the block scheme of the device. The proposed lvv random generator consists of a yV-bit shift register I, each bit of KOTOpiOro contains a trigger 1, a delay element 2, and an element razmi 3; adder modulo two II, containing the inverter 4, the circuit "And 5, the elements of differentiation 6 and the circuit" OR 7; matching unit I1, consisting of a differentiation element 6 and a delay element 2 and a forming unit IV, containing inverters 4 and a powerful trigger 5.

The generator works as follows.

Winding pulses arriving on bus A change the state of the shift register bits. At the same time, due to elements of isolation, the 3 shift register functions without failures with high stability.

The signals from the single outputs of the L / st and th bits of the shift register are fed to the inputs of the adder modulo g / v II, and the parity check is passed. The elements of the Modulo-2 adder due to the elements of differentiation 6 are free from mutually undesirable influences on the base current and provide a high stability of magnitude and a modulator two linear logic operation

f () Xk XN + Xi, XN

The parity-tested signals from the output of the modulo-two adder circuit are fed to the input of the matching unit III, which delays them for the duration of the clock and the time wave, and the DC link between the shift register I and the sum-POIM modulo two Ii. In this case, the differentiation element 6 of the matching unit performs an additional function — it forms the fronts and a pulse in reverse motion. From the output of the matching unit, the feedback pulses to the 1) post) are fed to the input of the first digit of the shift register, affecting the state of the shift register so that the state of any bit turns out to be subject to a pseudo-random law with a period of control pulses. The output of the pseudo-random sequence I1M | pulBSO (B is from the output of the formation blend ("Lemma B)", which is a powerful triggered 8, whose single inputs through the inverters 4 are connected to the single leads of the nth shift of the shift register). and neither a powerful trigger that repeats the information of the nth bit of the shift register to the tth bit of the shift register.

In the scheme of the shift register I, any triggers of / can be applied, made according to the scheme-e with separate backdrops. As delay elements 2, any delay lines can be used, which provide a pulse delay for a time equal to the duration of a TaiKTOBoro I1 pulse. Diodes can be used as isolation elements 3, each of which is connected by a plus to the common point of the circuit, and a minus to the input of the corresponding shift register bit. In the pseudo-random pulse sequence generator circuit, any differentiation elements may be used, for example, differentiating / C-chains.

Prevention Invention

Claims (2)

1. The P1sev1 to a random pulse trainer containing a register of the shift, the single outputs of the last and the / fe-oro bits of which are connected to the inputs of the modulo two adder, and the single outputs of the t-o, ro bits of the shift register, are connected to inputs of a shaping unit, characterized in that, in order to increase the stability of the generator, it contains an isolation element and a matching unit consisting of successively connected differentiation element and delay element, while the Bicex bits of the bits are connected through equal elements the total generator width, and the output of the modulo adder is connected to the input of the first register bit shift through the rematch block. 2. The generator according to claim 1, characterized in that the modulo-two adder contains two AND circuits, the outputs of which through the corresponding differentiation elements are connected to the OR inputs of the OR circuit, and the first B1 INPUTS of the circuits “And are connected respectively to the first and second inputs of the totalizer modulo two, the third input of which is connected to the second inputs of the circuits “And, to the first — directly, to the second — through the inverter.