SU422105A1 - MULTI-CHANNEL COUNTER PULSES - Google Patents

Description

one

The invention relates to discrete information processing devices and can be used in the construction of devices of automatic control systems, as well as measuring equipment, whose function is to count the number of pulses that follow several information channels.

A device is known that contains N information registers, a sum register with an input combinatorial circuit and a channel switch, the outputs of which are connected to the recording inputs of the corresponding information registers.

To build a counter on N information channels, it is necessary to apply N combinational circuits, which, with a significant N, leads to high costs for the element base, as well as to the complication of functional (electrical) connections.

The proposed device differs from the known fact that, in order to simplify the device, the outputs of the information register of each channel are connected to the inputs of the combinational circuit through the additionally introduced analyzer of the state of this channel, the second input of which is connected to the corresponding output of the channel switch, and the outputs of the register of the sum write all information registers.

The drawing shows the scheme of the proposed multi-channel pulse counter for the three information channels. The counter consists of four registers 1.

The outputs of three of them through analyzers 2 states of information channels, controlled by the outputs of the switch 3 channels and buses 4 information channels, are connected to the inputs of the combinational circuit 5. The output of the combinational circuit 5 is connected to the input of the fourth register 1. The output of the fourth register 1 through valves 6, controlled by a switch of 3 channels, connected to the inputs of three registers 1. A switch of 3 channels operates from control pulses received at its input via bus 7. The device operates as follows. The first control pulse via bus 7 is fed to the input of the switch 3 channels.

The leftmost (according to the scheme) output of the switch 3 channels is set to the state in which the outputs of the leftmost register 1 out of three are connected via the analyzer 2 channel states to the inputs of the combinational circuit 5. If there is a pulse on the bus 4, the combinational circuit 5 produces this next pulse with the previous number of pulses on the given information channel, and a new value of pulses

is written to the upper (fourth) register 1, and then from this register through valves 6 (recording gates of all information registers), at one input of which the resolving potential of the leftmost output of the switch of 3 channels is already present, is rewritten to the leftmost register 1 of three.

If there is no pulse on bus 4 of the information channel, then the state of the leftmost register 1 of the number three without conversion is transmitted through the circuit: register 1 - analyzer 2 of the information channel state - combinational circuit 5 - upper (fourth) register 1 - valves 6 - register one.

The second control pulse via bus 7 sets the average output of the switch 3 channels to a state in which the middle register 1 out of three is connected through the middle analyzer 2 of the information channel state to the inputs of the combinatorial circuit 5. Then, similarly to the described method, counting the number of pulses but the second information channel.

The third control pulse on bus 7 sets the rightmost output of the 3 channel switch to the state in which the number of pulses on the third information channel is counted, similarly to that described above.

The fourth control pulse on bus 7 nostunet to the input of the 3 channel switch, and the described cycle of sequential processing of the three channels is repeated.

As a result of the counter operation on each of the three registers 1, the number of impulses that have come but for each information channel is accumulated.

When building a counter on L information channels, the channel switch should have N outputs.

P ip e d eme and z about b & t e and u

A multichannel pulse counter for N channels, containing V information registers, a sum register with a combination circuit at the input, and a channel switch, whose outputs are connected to the write inputs of the corresponding information registers, characterized in that, in order to simplify the device, the outputs of the information register of each channel are connected to the inputs of the combinator circuit through the additionally entered state analyzer of the given channel, the second input of which is connected to the corresponding output of the channel switch, and the outputs Registers amount connected.

with write gates of all information registers.