SU416861A1 - - Google Patents

Description

one

The invention relates to analog-to-digital converters used by iB digital-measuring and control systems, in particular to converters from small time intervals of single pulses to a digital code.

The prior art device containing an iB of each bit is a reference delay line, the output of which through a coincidence circuit is connected to the trigger input, the output of which is connected to one input of the mismatch circuit, the other input of which is connected to the output of the reference delay line, is characterized by low accuracy.

The proposed new precision device contains an auxiliary delay line, an optional reference delay line and a Key, where the input of the reference delay line through the auxiliary delay line and the additional reference delay line is connected to one key input and to the output terminal, the other key input is connected to the output of a non-drop-off circuit , one of the outputs of which is limited: 1 to the input of the additional reference delay line.

The drawing shows a functional diagram of one bit of the proposed device.

Device sodernsnt line 1 and 2 delays with a delay time equal to the "weight of the bit, match 3 circuit, static trigger 4, mismatch circuit 5, auxiliary delay line 6, key 7. Delay time in line x 1 n 2 of the first converter bit is taken equal to half maximum by the duration of the measured signals 7p.ma - with the delay time in line 6 a little more than the sequential operation time; schemes 3 and 4.

If the length of the pulse to be measured is the stage delay of the cascade, then the input signal on delay lines b and 2 passes through the input following its cascade without conversions and does not change the initial zero state of the trngger. Potential from trigger output, donations; to the input of the mismatch circuit 5, it does not transmit a signal through it, and the key 7 is open.

If the duration of the measured impulse is longer than the cascade delay time, then the input and output linear delay 1 will create the conditions of the circuit operation to coincide - (. Lower 3. The signal from the output will throw the trigger 4 into one state. Line the delay 6 delays the passage of the signal through the delay line 2 for the response time of the circuit 3 1I of the trigger 4, thus eliminating the influence of these circuits on the measurement accuracy, while the rear part of the impulse passing from the delay line 6 to the input of the circuit 2 does not enables actuation Mismatch 5, and key 7 remains at 1 open time. As soon as the signal at the input of delay line 2 disappears, under the action of a single trigger of 4 trigger, match 5 opens key 7, short, the output of the delay line 2 to ground. Next, the cascade passes a pulse, for which its height is equal to Г „-Гзп, where Hz is the duration of the impulse received at the input of the n-th cascade. G - ,, ,, - is the delay time of the l-th cascade, i.e." weight this converter.

The state of the triggers of all bits after the passage of the impulse fixes the code of the pulse duration with an accuracy of up to the weight of the least recent last bit of the converter.

Subject and title

A time interval converter into a bit-coded: coding code containing in each bit a reference delay line, the output of which through a coincidence circuit is connected to the trigger input, the output of which is connected to one input of the pesovnadpei circuit, the other input of which is connected to (the output of the delay line, characterized in that, in order to increase accuracy, it contains an auxiliary delay line, an additional reference delay LIELD, and a key, with the input of the reference delay line through the universal delay line and the D01 field itelnuyu reference delay line connected to odno.mu input key and to the output: Clem-Th, d zugoy key input connected to the output circuit of mismatches, one of the inputs to the input of which nodklyuchen additional reference line Zadeh | rzhki.

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