SU410558A1 - - Google Patents

Info

Publication number
SU410558A1
SU410558A1 SU1710153A SU1710153A SU410558A1 SU 410558 A1 SU410558 A1 SU 410558A1 SU 1710153 A SU1710153 A SU 1710153A SU 1710153 A SU1710153 A SU 1710153A SU 410558 A1 SU410558 A1 SU 410558A1
Authority
SU
USSR - Soviet Union
Prior art keywords
bus
trigger
output
input
inverter
Prior art date
Application number
SU1710153A
Other languages
English (en)
Russian (ru)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to SU1710153A priority Critical patent/SU410558A1/ru
Application granted granted Critical
Publication of SU410558A1 publication Critical patent/SU410558A1/ru

Links

Landscapes

  • Logic Circuits (AREA)
SU1710153A 1971-11-01 1971-11-01 SU410558A1 (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU1710153A SU410558A1 (enrdf_load_stackoverflow) 1971-11-01 1971-11-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU1710153A SU410558A1 (enrdf_load_stackoverflow) 1971-11-01 1971-11-01

Publications (1)

Publication Number Publication Date
SU410558A1 true SU410558A1 (enrdf_load_stackoverflow) 1974-01-05

Family

ID=20491703

Family Applications (1)

Application Number Title Priority Date Filing Date
SU1710153A SU410558A1 (enrdf_load_stackoverflow) 1971-11-01 1971-11-01

Country Status (1)

Country Link
SU (1) SU410558A1 (enrdf_load_stackoverflow)

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