SU409366A1 - PHASE SENSITIVE ALTERNATING VOLTAGE CONVERTER IN DIGITAL CODE - Google Patents

Description

The invention relates to the field of electrical measurements in the range of infrasound and sound frequencies and can be used in determining the frequency dependence of the four-terminal transmission gains, in acoustic measurements, in the field of automatic control systems. A phase-sensitive variable-variable-to-digital converter is known, which contains a measuring frequency converter (ICP), a reversible pulse counter (RCI), a control node, and a readout device. However, the known device has an "accuracy of conversion" if there are harmonics of the operating frequency in the input signal. The purpose of the invention is to improve the accuracy of the conversion. This is achieved by the fact that in the proposed device, a frequency divider with several outputs is switched on between the ICP and RSI, and the control node contains the logic circuit "OR," AND and several trigger cells connected in series. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - diagrams, explaining the principle of operation of the device; TWA. Phase-sensitive converter sokit 1 measuring 1 frequency converter 1. frequency divider 2, control unit 3, consisting of l. "And, schemes 4 matches" And, schemes 5 "OR, source 6 of potential that controls the direction of the counting of the RSI, trigger cells 7, reversible counter 8 pulses, reading device 9. The following describes the design of the converter d / g 3. Outputs Matching circuits 4 in the converter's operation appear pulses (Fig. 2, a, b, c, respectively, the frequency of the others, where / "is the output instantaneous frequency of the PSI; .V / is the division factor of the 2 frequency divider relative to its output connected to / -and scheme 4 matches; / 1, 2, 3). The duration of each of the packs is selected in accordance with the timing diagram (Fig. 2) and is provided by the corresponding design of the trigger cells 7 of the control unit. The plots illustrate only the principle of operation of the converter; in a real device, each “pack” has more than 10 pulses. The bursts of pulses are summed by the 5 "OR circuit, the pulse sequence (Fig. 2, d) from its output goes to the counting input of RCI 8. Thus, the counting input of RCI 8 is at any time connected to one of the divider 2 frequency outputs, so The notion of the instantaneous frequency division factor N (Qt) between the output of the ICP 1 and the RCI input 8. The frequency divider 2 is made in the manner that L / C 15. The plot L (Qt) is shown in FIG. 2, d

At the input of the RSI Sj, the control of the counting direction, from the last trigger cell 7 of the control node, the potential I (Qi) is applied - FIG. 2, e. If R (Qt) O, then the RCI operates in the summation mode. Case R (Q: t) O corresponds to the readout value of the RSI.

In general, the result of phase-sensitive conversion of alternating voltage to digital code is represented by the integral

.. (t) o-t.

M

N (t) R (t) „,,, U) -vector

commutation

phase-sensitive transducer.

Sardinia (III) is shown “and FIG. 2, w. The attenuation in the C (W) of the higher harmonics of the main frequency — the approximation of G (Q /) to the sinusoidal function — improves the accuracy of the conversion in the presence of harmonics of the operating frequency in the input signal.

Subject invention

Phase-sensitive converter of alternating voltage to digital code. containing a measuring frequency converter, a reversible pulse counter, a control unit and a reading device, characterized in that, in order to increase the conversion accuracy, there is a frequency divider between the measuring frequency converter and a reversible pulse counter, and the control node contains the "OR matching schemes and connected in series trigger cells, the outputs of which are connected to the coincidence circuits, one of the inputs of each coincidence circuit is connected to the corresponding output the frequency splitter's outputs, and the outputs of the coincidence circuits - to the OR circuit, the output of which is connected to the counting input of the reversible pulse counter, the control input of the latter is connected to the output of the last trigger cell of the control node.

iiimiiHm

but

5 I I

g L

I I I I, Of