SU404088A1 - DEVICE FOR COUPLING DIGITAL COMPUTER MACHINE WITH EXTERNAL DEVICES - Google Patents

Description

The invention relates to computing and can be used in digital computers and systems.

The known devices for communicating external devices with a digital computer, the so-called multiplex and selector channels, perform information exchange operations between the main memory of the computer and its external devices. Their functions include the formation of signals "Chtenpe, Record, the numbers of the operative memory cell, the number of transmitted words, and others, as a result, the simultaneous and independent operation of external devices and the central processor is possible.

The known devices are characterized by a relatively low productivity of the computing system as a whole due to the significant expenditure of computer time for processing information that is transmitted over the communication channel between the central processor and external devices, especially when solving problems of an economic nature.

The purpose of the invention is to improve the performance of the computing system.

This goal is achieved by introducing into the communication device of a digital computer with external devices an additional control word register, an address modification block and an analysis block, the additional register being connected to the machine, the analysis block and, through the address modification block, to the address block, and the analysis block with a communications register and an address modification block.

The drawing shows a communication scheme of a digital computer with external devicesn.

A communication device of a digital computer with upstream devices consists of analysis block 1, address block 2, communications register 3, address modification block 4, control word register 5, an additional control register register word 6, and a interface block (buffer block) 7 .

As an example, a device operating in selector mode is considered.

which provides, at a given moment in time, a single external device with a chain-processor. When operating in multiplexed mode, junction blocks and additional control word registers are needed in an amount equal to the number of subchannels of the device.

The blocking is as follows. Through the communications register 3, information is exchanged between the central processing unit 8 of the computing system and the external

The device 9. Between the communications register and the external device, an interface unit 7 is inserted to match the information formats and electrical levels of the signals representing the information. The address block 2 generates a signal of the address code of the operative memory cell, its devices (RAM) of the central processor, with which information is exchanged, and also counts the number of words that have passed through the device after the operation has started. In the control word register 5, a control word is stored, which in known devices contains information about the initial address of the information in RAM, the number of RAM cells with which the exchange should be made, or the final address of RAM, the type of operation performed by an external device, such as input or output, as well as a number of other instructions on the organization of the exchange (for example, direct or reverse movement of the information carrier, word clutch, command clutch, etc.).

The additional control word register 6 is designed to store the operation code directly executed in the communication device of the digital computer with external devices, comparison conditions, analysis conditions, structure of the processed information, relevant information, as well as other necessary information about the process of converting high-level arrays through the device information.

The analysis unit 1 is designed to generate a control signal to the address modification unit 4. The control signal in the analysis unit is generated in accordance with the assignment to the comparison condition specified in the additional control word register 6.

The address modification block 4 is intended to change the address code in the address block 2 in accordance with signals that are not received from analysis block 1, and signals from additional control word 6 that carry information about the operation directly performed in the device.

Using the described device, one can carry out a series of operations of structural transformation of information arrays, which significantly relieve the CPU and in many cases greatly simplify programming.

The device works as follows.

It is assumed that the operation of the device prior to the introduction of additional equipment was provided and commands such as "Starting an external device are performed as well as earlier. Additional modes of the device are executed only if there are special codes in the additional register of the control word. This register contains information about the structure of the information array and how it is processed. Some of the operations are as follows:

a) a sample of the phrases of the array according to given characteristics;

b) the abbreviation of the array of phrases but given features;

c) selection from an array of information relating to the properties of the object, or suppression of this information;

d) shifted mode of operation, with sampling or abbreviation but featured with simultaneous suppression of relevant information in the resulting array, and some other modes.

When executing the operation “Sampling (reduction) of phrases of the array according to the signs, before entering the command“ Launching a device in block 6 from the central processor, the control will be entered

the word, in block 4, after decoding the operation code, the following sequence of signals is formed:

1) With the receipt of regular information in block 3, an impulse "Onros

block 1 according to which, in the case of the fulfillment of the conditions of comparison, given from block 1 to block 4, there is no response signal: "The current information corresponds to the given signs and conditions of comparison. By this signal, if the reduction mode is set, block 4 generates a series of signals, as a result of which the code of the RAM address contained in block 2 is changed so that the previously recorded message is erased by

information. When operating in sampling mode, a similar series is generated if the comparison conditions in the block 4 do not match.

2) The flow of information through communication devices always proceeds as usual, but

Unlike the normal mode, the change of addresses in the block of address 2 is abrupt, the hop direction is always the opposite, the magnitude of the jump is determined by the structure of the array, and the presence of information is determined by the information content and the specified mode of operation of the device.

The device mode “Sampling and suppression of information relating to certain properties of an object is similar to the one described above, but in this mode, an address jump, in nerves, is always one, second, it is enough to simply indicate the control word that this information should be excluded from array. Whereas in

The modes described above require the presence of the signal "The current information corresponds to the given characteristics. The offset mode of the device also occurs similarly to the first one, except that when you specify in the control word that the current information word is a unique value, i.e., it compares, the address jumps by 1 and in the generated array signaled information is suppressed.

Subject invention

The interface of the digital computer with external devices, containing, its communications register, connected to the processor and through the buffer block to external devices, control word register, connected to the processor, communications register and the buffer block, and the address block connected to a processor and a control word register, characterized in that, in order to increase the performance of the computing machine, an additional control word register, a block

modification of addresses and an analysis block, with the additional register of the control word being connected to the processor, the analysis block and through the address modification block to the address block, and the analysis block to the register

communication and address modification block.