SU390466A1 - DIGITAL PHASOMETER - Google Patents

Description

one

The invention relates to electrical measuring equipment.

A digital phase meter is known, consisting of two shaping devices, the inputs of which are connected (CO to instrument inputs; a controlled trigger; inputs of which are connected to the outputs of the shaping devices; the first and second key circuits and the meter connected in series, the time of the rear circuit consisting of series-connected a frequency divider and a tripper; a quantizing oscillator whose output is connected to the input of the first key circuit and a frequency divider, and the output of the trigger is connected to the input of the second key circuit.

This phase meter belongs to the class of averaging devices and is characterized by a large error in the measurement of -phase shifts between sinusoidal voltages subject to random phase modulation in the region adjacent to 0 ° on both sides.

In order to reduce the inconsistency of measuring phase shifts, the proposed phase meter is equipped with a third shaping device connected to the output of the controlled trigger; a delay line, an anti-coincidence circuit, and a first coincidence circuit, whose inputs are connected to the output of the third forming unit; a summing counter, the inputs of which are connected to the outputs of the second key circuit and the delay line, and the output to the input of the first coincidence circuit; the first group of keys, the inputs of which are connected to the outputs of the summing counter and the scheme of anti-holdings; subtractive counter, the inputs of which are connected in parallel to the inputs of the summing counter; the second group of keys whose inputs are connected to the outputs of the subtractive counter and the first matching circuit; an adder-indicator, the inputs of which are connected to the outputs of the first coincidence circuit and the anti-test circuit; a group of assembly circuits “OR, whose inputs are connected to the outputs of the first and second (Key groups, and the outputs to the inputs

adder indicator, the output of the first

match schemes. connected to circuit input

anti-coincidence.

To eliminate the ambiguity of reference

The proposed phase meter is equipped with a counter., the input of which is connected to the output of the first coincidence circuit, and the second coincidence circuit, the input of which is connected to the output of the counter and frequency divider, and the output to the adder indicator.

The drawing shows a block diagram of the described device, consisting of forming devices I, 2, 3, anti-coincidence circuit 4, controlled trigger 5, delay line 6, first 7 and second 8 matching circuits, key circuits 9, 10, summing counter 11 , the quantum generator 12, the first 13 and the second 14 groups of keys, the counter 15, the frequency div 16, the trigger 17, the group of the assembly circuits OR 18, the adder-indicator 19 and the subtracting counter 20.

The device works as follows.

The outputs Bxi and Bx are sinusoidal voltages, the phase shift between which is to be measured. Forming devices / and emit positive zero transitions of the input voltages and form pointed pulses at this moment. Under the influence of these pulses, the controlled trigger forms rectangular pulses, the duration of which is directly proportional to the measured phase shift and inversely proportional to the angular frequency of the signal. These rectangular pulses are fed to the input of the third forming device 2 and the first key circuit 9. The second input of the first key circuit 9 receives pulses from the quantizing generator 12. At the output of the first key circuit, a burst of pulses appears. These pulses pass through the second key circuit 10 during the measuring time generated by frequency divider 16 and trigger 17 from oscillations of the quantizing generator 12. Summing counter 11 stores the number of pulses in a burst, i.e. in one dimension. The Lomake number, corresponding to a phase shift of 360 °, is preliminarily recorded in the subtracting counter 20. Upon receipt of a burst of pulses subtractive counter 20 produces subtraction and remembers parity

max - 9

Where

N F; Y / 360g about

(T is the period of the input signal, and o is the period of the quantizing sequence). Forming device 2 extracts the moment of the end of the pulse generated by controlled trigger 5. B, if the number recorded in summing counter 11 is small, then the first coincidence circuit does not work under the influence of a pulse from the output of the third forming device 2. Then the anti-coincidence circuit 4 and outputs a pulse to the first group of keys 13 and the adder-indicator 19. Under the influence of this impulse, the adder-indicator 19 switches to the " add. The contents of the summing counter // through the key group 13 and the assembly circuit group “OR 18 will be added to the contents of the adder indicator 19. If, under the influence of the phase fluctuations of the input signals or when measuring large phase shifts, the contents of the summing counter 11 in some period exceed critical number. it works

first coincidence circuit 7. 180 ° phase shift

T

L.

 cr

2t

The summing counter 11 works in such a way that when a number is written into it, it gives the resolving potential to the first coincidence circuit. As a result of the operation of the first coincidence circuit 7, the adder-indicator 19 will be switched to the subtraction mode. Lomake difference is subtracted from the sum accumulated by the indicator-indicator 19 through the second rpyininy keys 14 and the group of circuits

assemblies "OR 18. After some delay, provided by delay line 6, in summing 11 and subtracting 20 counters, the initial conditions are restored. Since the numbers of the left half-plane as a result of the subtraction operation enter the adder-indicator 19 as the numbers of the right half-plane, there is an ambiguity of reference. As a sign by which you can eliminate the specified ambiguity,

should use the accumulated amount sign. Counter 15 counts how many times the first coincidence circuit 7 worked. In the case, if the number of operations exceeds half the number of all measurements,

determines the second coincidence circuit 8 by the pulse of the end of the measuring time from the frequency divider 16, then the adder 19 receives a signal to transfer the result to the region. If the number of operations of the first matching circuit 6 is less than half the number of all measurements, the result remains in the region.

Subject invention

Claims (2)

1. A digital phase meter containing shaping devices, a controlled trigger, key circuits, a quantizing oscillator, a time – master circuit consisting of a frequency divider and a trigger, characterized in that, in order to reduce the measurement error of phase shifts, it is equipped with a third shaping device connected to the output of a controlled trigger; the delay line, the anti-coincidence circuit and the first coincidence circuit, the inputs of which are connected to the output of the third forming unit; a summing counter, the inputs of which are connected to the outputs of the second key circuit and the delay line, and the output to the input of the first coincidence circuit; the first group of keys whose inputs are connected to the output; m of a summing counter and anti-coincidence circuit; subtractive meter inputs which are connected in parallel to the inputs of the summing counter; the second group of keys, the inputs of which are connected to the outputs of the subtractive counter and the first coincidence circuit; adder-indicator, the inputs of which are connected to the outputs of the first circuit matches and anti-coincidence patterns; “OR” input circuits, whose inputs are 1 connected to the outputs of the first and second pears of the keys, and outputs to the inputs of the adder-indicator, with the output of the first condominium scheme connected to the input of the ownership assets scheme. 2. Phase meter according to claim 1, characterized in that, in order to avoid counting ambiguity, it is equipped with a counter, the input of which is connected to the output of the first matching circuit, and a second coincidence circuit, whose input is connected to the output of the counter and frequency divider, and the output - to the adder indicator. 3, dl}