SU1004955A1 - Period duration digital meter - Google Patents

Description

The invention relates to digital measuring equipment and may be. used in the construction of precision frequency meters.

A device is known comprising ₅ reference oscillator, a shaper of quantizing pulses, a shaper of pulses of a measured frequency, a pulse counter, a pulse counter of a measured frequency, key C1]. 10

The disadvantage of this device is its low accuracy, which is limited by the stability of the frequency of the counting pulses, discrete error _{} 5} and the presence of noise in the input signal.

Closest to the present invention is a digital period meter containing a reference generator, formers of quantized pulses and pulses of a measured frequency, an adder, a pulse counter, a pulse counter of a measured frequency, keys. The output of the reference generator through the pulse generator and the key is connected to the input of the pulse counter, the device input through the pulse generator of the measured frequency is connected to the input of the pulse counter of the measured frequency and to the key synchronization inputs. The first output of the pulse counter of the measured frequency is connected to the control input of the key, and its second output is connected to the control inputs of the keys. The outputs of the pulse counter through, the keys are connected to the inputs of the accumulator type accumulator {2].

The disadvantages of this device are the relatively low reliability of its operation, which is due to the presence of a large number of trigger elements in the counting and register circuits and valves in the key circuits, the low accuracy of the device’s measurements is due to the synchronization of the process of summing pulses of the measured frequency, which can lead to the summation of false information at the moment coincidence in time of the quantizing pulse and the pulse of the measured frequency, as well as the fact that the measurement algorithm, which is implemented in a known manner property, does not allow to obtain the extreme accuracy provided by the weighted processing of the signal, since the formation of the final result does not involve the first period of the measured signal.

The purpose of the invention is to increase reliability and increase the accuracy of measurements.

This goal is achieved by the fact that in the device containing the reference generator, the output of which is connected * to the input of the counting pulse shaper, a pulse shaper of the measured frequency, the output of which is connected to the input of the pulse counter of the measured frequency and the first inputs of two keys, the second inputs of which are connected to the first and the second outputs of the pulse counter of the measured frequency, respectively, the adder and the pulse counter, introduced a memory register, a reversible counter and two ^ -triggers, 'A - the inputs of which are connected to the outputs with sponding keys C inputs are combined and connected to the output of the pulse shaper and to the counting input of the storage register of synchronization, -Log B connected to a bus signal logic '1', the inverted outputs of the first and second flip-flops soe-. are respectively respectively connected to the summing and subtracting inputs of the reversible counter, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the memory register, the input of which is connected to the output of the adder, the output of the transfer signal · of which is connected to the input of the pulse counter, the reset input of which is connected to initial setting bus and with reset inputs of a reversible counter, a memory register and a pulse counter of the measured frequency.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 - time diagrams explaining the principle of its operation.

The device comprises a reference generator 1, a shaper 2 of the counted pulses, a shaper of 3 pulses of the measured frequency, keys 4 and 5, for example, two-input elements And, a counter of 6 pulses of the measured frequency, D-flip-flops 7 and 8, which perform the functions of generating signals for summing and subtracting, reversible counter 9, adder 10, memory register 11, counter 12 pulses.

The device operates as follows.

Before the start of the measurement cycle, the reversible counter 9, the memory register 11 and the pulse counter 12 are set to zero using the initial setting signal. Pa inform15 inputs * [) —triggers and I of summing and subtracting signals, a constant logic 1 * level is supplied, for example, from the device’s power supply, which, under the action of quantizing pulses from the output of generator 1 (Fig. 26), acting on the C-inputs synchronization T) - triggers sets the latter to the state * Ί *, i.e. at the inverted outputs of the m-triggers there is a zero level (Fig. 2d, c). The passage of signals through the key 4 is placed by a signal of a unit level from the output of the counter of 6 pulses of the measured frequency (Fig. 2 c), 30 and the passage of signals through the key 5 is prohibited by the signal of the zero level from the output of the counter 6 pulses of the measured frequency (Fig. 2 g), which contains counter state decoder. Th entrances. the adder 10 from the outputs of the reversing counter 9 and the memory register 11 codes of zeros are received, and the summing result is also zero, for each quantizing pulse at the synchronization input of the memory register 11 it is rewritten to the last and again the pos-C goes to the second adder 10. In this case, the transfer signal the output of the adder 10 does not occur and the device continues to be in its original state.

The first pulse of the measured frequency from the output of the shaper 3 pulses of the measured frequency (in Fig. 2a - they are ⁵⁰ pulses with the number 1, goes to the output. Key 4 and from its output to the R-input. P-trigger 7, thereby setting on the inverse the output of trigger 7 is a single level and blocking the action of 55 quantizing pulses at the synchronization input of the D-trigger 7 (Fig. 2 e). After the pulse of the measured frequency at the R, input J) ends, the trigger 7 of the summing signals is the first quantizing next the pulse arriving at the C-input T) -trigger 7, sets n Latter in one state (FIG. 2 d /.

Thus, a pulse is generated at the output of the B-trigger, hera 7 (Fig. 2 e), the leading edge of which is determined by the leading edge of the measured frequency pulse, and the trailing edge by the falling edge of the quantizing pulse (the B-trigger 7 is triggered by the leading edge of the signal at R-input and on the trailing edge of the signal acting on the C-input), which allows you to synchronize the processes of summation in the adder 10 and the formation of the code at the output of the reversing counter 9. This pulse is applied to the summing input of the reversing counter 9 and sets at its output, binary code 1, which is fed to the first input of adder 10. The result of the summation for each quantizing pulse is written to the memory register 11 and from its output is applied to the second input of adder 10. That is, for each quantizing pulse, the contents of register 11 increase memory per unit. The adder 10 sums the numbers modulo N, and the pulses from the output of the transfer signal are fixed. there are 12 pulses in the counter. The second pulse (Fig. 2 a) of the measured frequency passes to R. The input of the D trigger 7, and, similarly to the first pulse, together with the first quantizing pulse following it, forms a signal at the inverse output of the E trigger 7, which is fed to summing the input of the reverse counter 9 and sets the binary code of the number * 2 at its output. Now during the time interval (Fig. 2, a) there is an increase in the contents of the memory register 11 and the counter 12 pulses by two for each quantizing pulse. So, it occurs before the Kth pulse of the measured frequency (Κί ψ for even ft, where

P is the number of measured pulses, with odd i), which sets the code of the number K at the output of the reversing counter 9 and, entering the input of the counter 6 pulses of the measured frequency, removes the signal of a unit level from the input of the key 4. Now, during the time interval from the Kth pulse to (i-K) -th pulse of the measured frequency of change

1004955 6 f the state of the reverse counter 9 does not occur, and for each quantizing pulse, the contents of the memory register 11 and the counter of 12 pulses per K. are increased. The (and –K — 1) pulse of the measured frequency arrives at the input of the counter 6 pulses of the measured frequency and sets it at the input key 5 signal unit level. Therefore (I-K), the pulse of the measured frequency passes to the output of the key 5 and, therefore, to the R-input D of the trigger 8, forming together with the first, next on it, quantizing pulse at the output of the D-trigger 8 signal (Fig. 2 e ), which is fed to the subtracting input of the reversible counter 9. At the same time, the code of the number (K-1) is set at the output of the reversible counter 9, by which the contents of the memory register 11 and the counter 12 pulses are increased each; quantizing impulse during the (i-K) -th period of the measured frequency. (i-K + 1) —th pulse of the measured frequency sets the number code (K-2) at the output of the reverse counter 9, etc. to the fifth pulse of the measured frequency, which sets the zero code at the output of the reverse counter 9. Moreover, the increase in the contents of the register 11 of the memory and counter 12 pulses; in which a number is fixed proportional to the length of the period of the measured signal, stops until the start of the next measurement cycle.

In accordance with the described algorithm, the result recorded in the memory register 11 and pulse counter 12 is expressed as follows where Tg- is the duration of the measured period;

T. K - duration

1ιΤ '· do adjacent intervals between pulses.

When comparing the measurement accuracy of the known and the given device with respect to the standard errors, we obtain at K = an increase in the measurement accuracy.

In addition, the device contains times, where T _x is the maximum measured period;

That is the period of the pulses of the reference generator, a smaller number of vent1004955 lei compared with the known devices.

Due to the fact that the trailing edge of the pulses at the summing and subtracting inputs of the reversing counter 9 is formed by quantizing pulses and the processes of summing and generating a code at the output of the reversing counter 9 are synchronized, device malfunctions are excluded when the measured frequency pulses and the quantizing pulses coincide in time.

Thus, the introduction of new elements and the relationships between them can significantly improve the reliability of the device and the measurement accuracy.

Claims (2)

(54) DIGITAL MEASUREMENT OF DURATION The invention relates to digital measurement technology and can be. used in the construction of precision frequency meters. A device containing is known. reference oscillator, quantizing pulse shaper, measured frequency pulse shaper, pulse counter, measured frequency pulse counter, key Cll The disadvantage of this device is its low accuracy, which is limited by the frequency stability of the counting pulses, the random discreteness and the presence of noise in the input signal . The closest to the proposed invention is a digital period duration meter, comprising a reference oscillator, shapers of quantizing pulses and pulses of a measured frequency, an adder, a pulse counter, a counter of impulses of a measured frequency, and keys. The output of the reference oscillator through the quantizing pulse shaper and the key is connected to the pulse count center BHOTS, and the input of the device through the pulse shaper of the measured frequency is connected to the pulse frequency counter BXCVIOM and to the inputs of the sync keys. The first output of the pulse meter measuring frequency is connected to the control input of the key, and its second output is connected to the control inputs of the keys. The outputs of the pulse counter through, the keys are connected to the inputs of the accumulator accumulator type J2. The disadvantages of this device are relatively low reliability of its operation, due to the large number of trigger elements in the counting and register circuits and gates in the key circuits, the measurement accuracy of the device is low due to the synchronization of the process of summing the measured frequency pulses, which can lead to the summation of false information at the time of coincidence of the quantizing impulse and the impulse of the measured frequency, and also by the fact that the measurement algorithm, which is realized in the known device This does not allow us to obtain the maximum accuracy provided by the weight processing of the signal, since the first period of the measured signal does not take part in the formation of the final result. The purpose of the invention is to increase reliability and increase accuracy. The delivered pel is achieved by the fact that a device containing a measuring generator, the output of which is connected to the input of the counting pulse generator, a pulse shaper of the measured frequency, the output of which is connected to the input of the pulse counter of the measured frequency and the first inputs of the two keys, the second inputs of which are connected to the first and the second outputs of the pulse counter of the measured frequency, cooTBetcTBeHHO, the summator and the pulse counter are outputted by the memory register, the reversible counter and two triggers, / I - whose inputs are connected to the outputs of the keys, the inputs are combined and connected to the output of the counting imprinter 5v generator and to the memory register synchronization input, and the .D inputs are connected to the signal bus, the inverse outputs of the first and second triggers are connected respectively to the summing and subtracting inputs of the reversible counter, the output which is connected to an adder input of the adder, the second input of which is connected to the output of the memory register, the input of which is connected to the output of the adder, the output of the transfer signal which is connected to the input of the pulse counter, input mildew which is connected to the bus with the initial setup and reset inputs of down counter register memory -u counter pulse frequency being measured. FIG. 1 shows a block diagram of the device; in fig. 2 - timing diagrams, explaining the principle of its work. The device contains a reference oscillator 1, a shaper 2 counting pulses, a fork rapper 3 pulses of the measured frequency, switches 4 and 5, S54, for example, two-input elements And, a counter of 6 pulses of the measured frequency, D-triggers 7 and 8, performing the functions of summing signals and subtract, reversible counter 9, adder 10, memory register 11, pulse counter 12. The device works as follows. Before the start of the measurement cycle, the reversible counter 9, the memory register 11 and the pulse counter 12 are set to the zero state by means of the initial setting signal. Informational INPUTS DD-triggers 7 and ti of the summation and subtraction signals are supplied with a constant level of logic 1, for example, from a device power supply which, under the effect of quantizing pulses from the output of generator 1 (Fig. 26), acting on the C synchronization inputs D Triggers set the last to state 1, i.e. on the inverse outputs of D-triggers there is a zero level (Fig. 2, e). The passage of signals through key 4 is placed by a single level signal from the output of the counter 6 pulses of the measured frequency (Fig. 2c), and the passage of signals through the key 5 is prohibited by a zero signal from the output of the counter 6 pulses of the measured frequency (Fig. 2g), which contains a counter state decoder. Both the inputs of the adder 10 from the outputs of the reversible counter 9 and the memory register 11 receive codes of zeros, and the result, sum 1, also zero, for each quantizing pulse at the input of the sync memory 11, the memory register 11 is rewritten into the last and again to the second summer adder 1O. In this case, a transfer signal does not occur at the output of the accumulator 10 and the device continues to be in the initial state. The first pulse of the measured frequency from the output of the imager 3 pulses of the measured frequency (in Fig. 2a - pulse number l passes to the output of the key 4 and from its output to the R-input 3 of the trigger 7, thereby setting on the reverse output of the trigger 7 unit level and blocking the effect of quantizing pulses at the synchronization input) - trigger 7 (Fig. 2 d). After the end of the pulse of the measured frequency at R, input 3), the trigger 7 of the summing signals, the quantizing pulse following it, arriving at the C input of the D trigger of 7, sets the latter into one state (Fig. 2 d) .. Thus, at the output of the D-trig, hera 7 a pulse is formed {fig. 2 e) the leading edge of which is determined by the leading edge of the measured frequency pulse, and the falling edge - by the falling edge of the quantizing pulse (the trigger of the D trigger 7 occurs on the ample edge of the signal at the R input and on the falling edge of the signal acting on the C- input), which makes it possible to synchronize the processes of summation in the adder 1O and the formation of a code at the output of the reversible counter 9. a pulse arrives at the summing input of the reversible 9 and is set up & At its output, binary code 1 is fed to the first input of the adder 10. The result of the summation for each quantizing pulse is rewritten into memory register 11 and applied from its output to the second input of the adder 10. That is, for each quantizing pulse, the content increases. register 11 memory per unit. The adder 1O sums the numbers modulo N, and the pulses from the output of the transfer signal are recorded in the counter 12 pulses. The second pulse (4air. 2 a) of the measured frequency passes through K .-. The input of the D-flip-flop 7, and, similarly to the first pulse, with & the first one following the quantizing pulse, forms on the inverse output of the D-trigger 7 sig It arrives at the summing input of the reversible counter 9 and sets at its output the binary code of the number 2. Now during the time interval Tj. (Fig. 2a), the contents of the memory register 11 and the pulse counter 12 are increased by two for each quantizing pulse. So, up to the K-th pulse of the measured frequency (K 5 for even and C is the number of measured pulses, X5 for odd and), which sets at the output of the reversible counter 9 a code of the number K and, arriving at the input of the counter 6 pulses of the measured frequency, removes a single-level signal from the key 4 input. Now, during the time interval from the K-th pulse to the (and-K) -th pulse of the measured frequency, a change in the state of the reversing counter 9 does not occur and for each quantizing pulse the content increases register 11 memory and count Single pulses at 12 C. (i-K-1) pulse measured by the frequency received at input 6 of the counter pulse frequency being measured, the unit 5 sets the signal level on the input key. Therefore, the (MK) impulse of the measured signal passes to the output of the key 5 and, therefore, to the I-input 3) -trigger 8, together with the first quantizing impulse at the output D - the trigger 8, forms a signal (FIG. 2 e), which is fed to the subtracting input of the reversible counter 9. At the output of the reversible counter 9, a code of the number (K-1) is set, by which the contents of the memory register 11 and the counter of 12 pulses each increase: a quantizing pulse during (and-K) -th period of the measured frequency. (I-K + 1) -and the pulse of the measured frequency sets the code of the number K-2 at the output of the reversing counter 9, etc. to the output pulse of the measured frequency, which sets the zero code at the output of the reverse counter 9. At the same time, an increase in the contents of the memory register 11 and the pulse counter 12; in which a fixed number proportional to the duration of the permeable signal is stopped until the beginning of the next measurement cycle. According to the described algorithm, the result registered in the memory register 11 and the pulse counter 12 is expressed as follows: + U - i) V, -... + T ,,, where T is the duration of the measured period; T. l ,,. the duration of the intervals between adjacent pulses. When comparing the measurement accuracy of a known and a given device with respect to the mean-square error, for K, an increase in the measurement accuracy is obtained. In addition, the device contains Water and T y d / 2 Toraz, where the maximum period is 1 measured period; TO - period of the pulses of the reference generator, the moving number of gates in comparison with the known device. Due to the fact that the leading edge of the pulses at the summing and subtracting inputs of the reversing counter 9 is formed by quantizing pulses and the processes of summing and forming the code at the output of the reversing counter 9 are synchronized, the malfunctions in the operation of the measured frequency and quantum pulses are eliminated. Thus, the introduction of new ele св amps and the connections between them makes it possible to significantly increase the reliability of the device and the measurement accuracy. DETAILED DESCRIPTION OF THE INVENTION A digital period duration meter comprising a reference oscillator, the output of which is connected to the input of the counting pulse former, the pulse generator of the measured frequency, the output of which is connected to the input of the pulse counter of the measured frequency and the first inputs of the two keys, the second inputs of which are connected to the first and second outputs a pulse counter of the measured frequency, respectively, an adder and a pulse counter. Namely, in order to increase reliability and increase measurement accuracy, a memory register, a reversible counter and two D triggers are entered into it, 1 - inputs, which are connected to the outputs of the corresponding keys, C-inputs are combined and connected to the output of the imager counting pulses and to the input of synchronization memory register, and D-inputs are connected to a logic signal, inverse outputs of the first and second triggers are connected respectively to the summing and subtracting inputs of the reversible counter, the output of which is connected to the first the adder stroke, the second input of which is connected to the output of the memory register, the input of which is connected to the output of the adder, and the output of the transfer signal of which is connected to the input of the pulse counter, the reset input of which is connected to the bus: initial setting and to the reset inputs of the reversible counter, memory register and a pulse counter of the measured frequency. Sources of information taken into account in the examination 1.Ornatsky P. P. Automatic measurements and instruments. Kiev, Vishcha School, 1980, p. 373. 2. USSR author's certificate number 661382, cl. G04 P-10 / O4, 1979. 1se (u s n: s