SU370712A1 - ALL-UNION ""} iATZh'TuD-- RTNGHG ^ RGude '^' ^^ KAYA_b :: blio- | -e.na MB AV. A. Kosinsky, Yu. K. Sudyin and A. P. Evdokimov - Google Patents

Description

one

This invention relates to the field of computing.

The four-phase dynamic // is known (- a trigger on MOS transistors containing two inverters, an assembly K. with an output assembly, an assembly / with a nerve output coincidence circuit, two inverters, a second coincidence circuit.

The aim of the invention is to increase the reliability and speed of the device.

For this, in the proposed device, the input of the output assembly and the input of the first matching circuit are connected to the nerve output bus of the trigger, the output of the first matching circuit is connected to the first input of the second matching circuit, the second input of which is connected through the first inverter to the output of the output assembly, the output of the second matching circuit is connected to the second output bus trigger and through the second inverter - with the first output bus trigger.

The device contains inputs 1, 2, 3, 4, input bus 5 of the power supply, outputs 6, 7 of the trigger, MOS transistors 8-23, logic circuits 24, 25 (assemblies K and I, respectively).

Suppose that in the initial state, output 6 has a potential close to the potential of the earth, output 7 is a note of ETs close to the potential of the power source, and logic circuits 24 and 25 operating in the key mode are open, which corresponds to a logical zero (therefore, the sources transistors 12 and 18 are not grounded).

npiH input to the input / phase F1 transistors 8 and 9 will be open. The input capacitances 26 and 27 of the transistors 19 and 20 are charged approximately to the potential of the power supply. When the phase of the phase arrives at the input 2, the transistor 2 will be opened through a series-connected transistor 17. The transistor 17 is open due to the presence of a negative potential at its gate, fed through feedback to the output 7.

Thus, the input capacitance 26 is discharged to approximately the potential "ground." Phase 2 opens the transistor 10 and the 2S capacitance of the transistor 22 is charged approximately to the potential of the power supply.

When arriving at the input 3 of the phase pulse fz, the transistor 13 will be closed because the transistor 18 connected in series with it is closed, because the source of the transistor 18 is not connected to the ground bus. On the input capacitance 27 of the transistor 20, a negative potential is maintained, corresponding to a logical one. The transistor 11 opens as a flux enters, and the input capacitance 28 of transistor 23 is charged to approximately

power source potential. Transistor

14 when it arrives at its gate, fz will be closed, since transistor 19 is connected in series with it (at the gate, the potential corresponds to a logical “zero”).

Consequently, at the input capacitance 29 of the transistor 22, a potential corresponding to a logical "unit" is stored.

When a phase pulse f4 arrives at input 4, transistor 15 opens, since transistors 20 and 22 connected in series with it (on gates of which the potential is approximately equal to the potential of the power supply).

Consequently, the input capacitance 28 of the transistor 23 is charged to a potential approximately equal to the potential of the ground. The traesistor 16 opens as the f4 arrives and the input capacitance 30 of the transistors 17 and 18 is charged to approximately the potential of the power source.

The phase f1 of the next tetrad of phasing pulses F1-f4 enters / enters. In this case, the transistor 21 will be closed, since the transistor 23 connected in series with it is closed (at the gate the potential is approximately equal to the potential “ground”). Input eiMKOiCTb 30 TpaH3iHCTqpoe 17 and 18 maintains a potential approximately equal to the potential of the power source.

Therefore, when the logic zeros are applied to both inputs, the trigger retains its state.

Suppose that by the time of arrival F1 logic circuit 24, operating in the key mode, is open, which corresponds to the logical "zero, and circuit 25 is closed, which corresponds to the logical" one.

In phase F1, capacitances 26 and 27 of transistors 19 and 20 are charged approximately to the potential of the power supply. When phase f2 arrives at input 2, capacitance 26 of transistor 19 is charged approximately until the ground through transistor-connected transistors 12 and 17. Transistor 17 is open, because the gate has a negative potential supplied by feedback from output 7. Phase capacitance 28 of the transistor 22 is charged to approximately the potential of the power supply. Upon receipt of the phase fz at the input 5, the capacitance 27 of the transistor 20

discharges approximately to ground potential through series-connected transistors 13 and 18. Transistor 18 is open, because the gate has a negative potential applied by feedback from output 7, and the source is connected to ground through a closed key 25. Phase capacitance 28 transistor 23 is charged approximately to the potential of the power source through the transistor //. Until the end of this phase pulse, capacitance 29 maintains a potential approximately equal to the potential of the power source, since transistor 19 is closed, due to the presence on its gate of a potential approximately equal to potential ground. When phase FD arrives at input 4, transistor 15 will close because transistor 20 connected in series with it (the potential at the gate is approximately equal to the potential of the power source). In phase 4, a transistor 16 is opened, and the capacitance 30 of transistors 17 and 18 is closed approximately to the potential of the power supply. When phase F1 arrives at the input / transistor 21 and the transistor 23 connected thereto5

open, and the capacitance 30 of the transistors 17 and

18 is charged to approximately the potential

“Land

Thus, the trigger changes its state.

The trigger operation for other input combinations x / and / C is similar.

Subject invention

Four-phase dynamic // (- trigger on MOS transistors containing two inverters, assembly / C with output assembly, assembly / with the first output matching circuit, two

inverter, the second coincidence circuit, characterized in that, in order to increase reliability and speed, in it the input of the output assembly and the input of the first coincidence circuit are connected to the first output trigger bus, the output of the first coincidence circuit is connected to the first input of the second coincidence circuit, the second input of which connected via the first inverter to the output of the output assembly; the output of the second coincidence circuit is connected to the second

output length (pa and through the second inverter) is the output trigger length of the trigger.

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