SU369590A1 - DIGITAL INTEGRATOR - Google Patents

Description

one

The proposed digital integrator refers to digital computing devices in which function increments are used to calculate the integral.

Known digital integrators of sequential type, containing adders and registers. However, such schemes, with sequential processing of each bit of functions and increments, have a large integration time.

The goal of the inventive invention is to increase the speed and accuracy of a digital integrator.

In the proposed digital integrator, this goal is achieved by using parallel registers and adders, and also by using two parallel adders to multiply the increments, which combine control signals into one adder to add and multiply functions.

The drawing shows a block diagram of the integrator.

The buffer register U is the register through which the digital integrator exchanges information. The outputs of the buffer register are connected to the inputs of the first register of the multiplicand 2 for transmitting the increments of the integrand function, the higher bits of the integrand function, and the higher bits

the remainder. The outputs of the buffer register / are also connected to the inputs of the first register of the multiplier 5 for transmitting the increments of the variable integration. In addition, the outputs of the buffer register are connected to the inputs of the second register of the multiplicand 4 for transmitting the increments of the integrand function and the lower bits of the remainder. The connection of the outputs of the buffer register Y with the inputs of the second register of the multiplier 5 is used to transfer the increments of the variable integration. The outputs of the first register of the multiplicand 2 through the valves 6 multiplying the first adder 7 are connected to the inputs of the intermediate register S of the first adder in such a way that, depending on the control signal supplied from the outputs m of the lower bits of the second register multiplier 5, to the control inputs of the multiplication gates 5 the first adder, the number written in the first register of the multiplicand 2 can be transmitted either in the forward code or in the additional code or shifted to the left, i.e. multiplied by tons of lower digits of the number

the second register. multiplier 5. Similarly, the outputs of the second register of the multiplicand 4 through the valves 9 multiplying the second adder 10 are connected to the inputs of the intermediate register // second adder in such a way that

depending on the control signal supplied either from the outputs of the low-order bits of the first register multiplier 3, or from the outputs of the low-order bits of the second register multiplier 5 to the control inputs of the gates 9 multiplying the second adder W, the number recorded in the second register of multiplicand 4, may be transmitted either in the forward code, or in the additional code, or with a shift to the left. The outputs of the intermediate register 8 of the first adder 7 are connected to the inputs of the first adder, and the outputs of the intermediate register 11 of the second adder 10 are connected to the inputs of the second adder.

The first register of the multiplier 3 and the second register of the multiplier 5 are shift registers in which information can be shifted to the right by m bits, with the outputs t of the lower bits of the first register and the multiplier 3 through the control, and the shift valves 12 are connected by a shift circuit with t older the bits of the second register of multiplier 5, so that these registers can, depending on the control signals supplied to the shift control valves 12, be combined into one shift register to multiply the number in the first register of the multiplicand 2 by the numbers about finds luminant in the combined shift register, or for multiplying the number, the older bits which are in the first multiplicand register 2, and the lower - in the second multiplicand register 4, the number in the combined shift register.

The outputs of the first register of the multiplier 3 are connected to the inputs of the buffer register / for issuing information from a digital integrator. In addition, the outputs of the first register of multiplier 5 are connected to the inputs of the second adder 10 for summing full-digit numbers. The outputs of the first register of the multiplier 3 are connected to the inputs of the second register of the multiplier 5 for transmitting numbers.

For intermediate information storage, the outputs of the first adder 7 are connected to the inputs of the higher bits of the intermediate register 13 (the outputs of the same bits of the intermediate register 13 are connected to the inputs of the intermediate register 8 of the first adder 7). The outputs of the second adder 10 are connected to the inputs of the lower bits of the intermediate register 13 (the outputs of the same bits of the intermediate register 13 are connected to the inputs of the intermediate register // of the second adder 10).

The first adder 7 with its outputs is connected to the inputs of the first register of the multiplicand 2 so that the higher bits of the full-digit number located in the first and second adders 7 and 10 can be transferred from the first adder 7 to the first register of the multiplicand 2 for subsequent multiplication or summation. For the same purpose, the outputs of the second adder 10 are connected to the inputs of the second register of the multiplicand 4.

To save the low bits of the product, the outputs m of the lower bits of the first adder 7 are connected to the inputs m of the higher bits of the first register of the multiplier 3. For the same outputs, the m lower bits of the second adder 10 are connected to the inputs of the second bits of the second register of the multiplier 5.

The outputs of the first and second adders are connected to the inputs of the buffer register / for outputting information from the digital integrator. In order to transmit the higher product bits for subsequent summation, the outputs of the second adder / O are connected to the inputs of the first multiplicative register 2. The outputs m of the higher bits of the second adder are connected by transfer chains through the transfer control valves 14 with the lower bits of the first adder 7. This allows It is not possible to combine at the right time the first and second adders into one adder.

The proposed digital integrator can perform the following numerical integration algorithm; square parabola method

V .i) (ur, + Y 7 Уpk ,,) V y ,, JJ

+

+ - (V ur ,,, v y ,,, - v ur ,, v y ,, +

+ 0 .. ,,

which is performed in the following sequence:

P., 7U ,,,,

n, Vyp ,, - Vy ,,, j, 2. P, -P,

-nkS ..

2, gp, + o ,,,

Vi P "(; 4l) Zj Pi + T (+ 1)

. + bFor implementing the trapezoid method

) vy, v, i) +

/,one)()

+ 0,

g

PARTIES 4, 5, B of the algorithm (2) are fulfilled.

Algorithm (2) is implemented in the digital integrator in the following sequence. The control device, which is not shown in the diagram, is supplied with a sequence of control signals, which, in the buffer

register 1 from the storage device increments ypki and Vz / ps are received. The Vi / pu increment is then transmitted to the first register of the multiplicand 2, and the Vz / ps increment is

in the second register of the multiplicand 4. After that

the buffer register / receive increments Vyqkf and, whence the increment

then transferred to the first register of the multiplier 3, and the increment Vz /, to the second register of the multiplier 5.

Thereafter, a simultaneous multiplication of the increment ypkn + iy in the first register of the multiplicand 2 begins, by the increment of Vt / gki, in the second register of the multiplier 5, and the increment of ypk {, which is in the second register of the multiplicand 4, by the increment of Vz /, first multiplier 3.

Receipt of

n: Vy; ,,, ft,

occurs as follows.

In accordance with the code recorded in the m lower bits of the second register of multiplier 5, the increment in the first register of multiplicand 2 is transmitted through multiplication valves 6 of the first adder 7 and the intermediate register of the first adder is transmitted to the adder with a forward or reverse code or with a shift to the left.

Then, the increment of Vtjqki, located in the second register of the multiplier 5, is shifted by t bits to the right, while the contents of the first adder 7 are shifted to the right bits by the right, and the lower bits from the adder are written to the high bits of the first register of the multiplier 3.

After this multiplication is repeated for a certain time, until the value of TT is obtained.

After the end of the multiplication, the leading bits of the product P1 are located in the first adder 7, and the lower bits in the first register of the multiplier 3.

Similarly, in the second adder 10, the increment of Vt / D, multiplied by 4 in the second register, is increased by the increment of multiplier 3 in the first register. After multiplying, the high bits of the product Pz are located in the second adder 10, and the youngest - in second register multiplier 5.

To obtain the difference Ei ni-Tlz, the highest bits of the product Uz are transferred from the second adder 10 to the first register of the multiplicand 2, and the lower bits from the second register of the multiplier 5 to the second register of the multiplicative 4. The first and second adders 7 and 10 feed the control signals the transfer control valves 14 are combined by one adder.

The minor bits of product P1 from the first register of multiplier 3 are transmitted to the second adder 10, then the product Pg through gates 5 and 9 multiplying the first and second adders 7 and 10 and the intermediate registers 8 and 11 of the first and second adders in the first and second adders Pi to get the value

P,..

the difference Si from the first and second adders is rewritten into the first and second registers of a multiplicand 2 m. 4. At the same time from the buffer register / into the first and second registers of a lot of 1

J and o are recorded in binary number (the most significant bits are written to the first register of multiplier 3, and the least significant bits are written to the second register of multiplier 5).

Through the shift control valves 12 on the control signal, the first and second registers of the multiplier 3 n 4 are combined into one shift register.

During multiplication, the younger ones are analyzed.

one

bits of the number found in the second

register multiplier 5. The result of the analysis is transmitted to gates 5 and 9 multiplying the first

and the second adders, through which the multiply is transmitted to the weave registers of the first and second adders and then to the first and second adders. Then the multiplier is shifted in the first and second registers of the multiplier 5 and 5 by m bits. The multiplication cycle repeats a certain time until the formation of the value of Pz.

During multiplication, the buffer register / the remainder of the integral obtained at the previous step is fed. After the multiplication is completed, the Ozki residue from the buffer register / enters the second multiplicand 4 and then through the multiplication valves 5 of the second adder and the intermediate register of the second adder is summed in the combined first and second adder with the value of P, to the form So,. The summation result is written from the adders to the intermediate register 13 for intermediate storage.

To form the new value of the integrand

 Ur (1-1) +

55

the increments Vr / pft,.,) and Vz / p from the storage device enter the buffer register /, whence Vy ,, i; is sent to the second register of multiplier 5, and Vr / pj jj is sent to the first register of integer 3. Next, i / rft () is written to the buffer register / and then

the higher bits of the integrand are rewritten into the first multiplicand register.

7

2, and the youngest ones are in the second register of the multiplicand 4. whence the function ypk,) through gates 6 and 9 multiply the first and second adders and intermediate registers of the first and second adders in the first and second adders with the VJ / PU increment issued to the second adder 10 from the second register of the multiplier 5. Then t / ps is written from the first and second adders to the buffer register} to output the new value of the integrand function to the memory, as well as to the first and second registers of the multiplicand 2 and 4. Simultaneously, the increment Vi / pft () shift a first register in the multiplier 3 on one bit to the right, the image size - Vi / pA (, - + j), is overwritten in the second

register multiplier 5 for further summation with ypki. Through valves b and 9 multiplying the first and second adders and intermediate registers of the first and second adders ypki is summed up on the first and second

increment adders — V (/ pft (;, j, in register 5, to form

S

g - yPkt + URK (1 + 1G

The resulting amount is rewritten from the first and second adders to the first and second registers of the multiplicand 2 and 4. Simultaneously from the intermediate register 13 to the intermediate registers of the first and second adders the value Ez is rewritten, from where it is written to the first and second adders 7 and 10.

At the same time, the increment Uchsh + i is entered into the buffer register / from the memory device. From the buffer register it is sent to the second multiplier 5.

After that, the multiplication of the value of EZ, located in the first and second registers of multiplicative 2 and 4, by the increment), located in the second register of multiplier 5, begins. Since by this time the value 22 was written in the adder, the resulting increment

V2 ,, + j) S3Vi /,., + 2.

or, taking into account the expression (2),

V2ft (, - + i) + - Vypft (i,) (i + i)) +

+ - (- ypit X

12

X 7Uqkf l + Ozk

After the end of multiplication, the increment of the integral Vz.jj is transferred to the buffer register} and then to the storage device for further use.

Subject invention

A pythic integrator containing a buffer register, the outputs of which are connected to the first and second registers of the multiplicand and multiplier, the output of the first pegister of the multiplicand through gates, the second inputs of which are connected to the second register of the multiplier, is connected to the intermediate output of the first register multiplier. a buffer register, the second one with shift control valves,

the outputs of which are connected through the second register of the multiplier to the second register of the multiplicand, and the third with valves, the second and third inputs of which are connected with the second registers of the multiplicand and multiplier, and the outputs with the intermediate register of the second adder; the output of the intermediate register of the first adder is connected with the first adder, the outputs connected to the first registers of the multiplicand and multiplier, to the buffer register; the output of the intermediate register of the second adder is connected to the second adder, outputs connected to the buffer register, to the second multiplier and multiplier registers, and to the transfer control valves, whose outputs are connected to the first adder, characterized in that, in order to improve speed, the accuracy of calculation, it contains an additional intermediate register, the inputs connected to the first and second adders, and the outputs - to the intermediate registers of the first and second adders; the third and fourth outputs of the first multiplier register are connected respectively to the second adder and the second

a multiplier register whose outputs are associated with a buffer register and with a second adder output connected to the first multiplicator register.