SU368601A1 - DEVICE MANAGEMENT MULTIPLICATION AND FISSION - Google Patents

Description

one

The invention relates to computing.

A device for controlling the multiplication and division of binary-decimal numbers in electronic computing keyboard machines, in which numbers are represented in dynamic-type registers in fixed-point form, the position of which is chosen by the operator using a special switch.

Known are the control units for multiplying and dividing binary-ten numbers, represented in the variable-fixed-point form, in an arithmetic unit on dynamic registers, including a clocking block with outputs of clock pulses associated with the local counter shadow input, a comma control switch, information shift control trigger and local control counter.

The proposed device is characterized in that it contains a ' tag entries, a tag extraction circuit and a tag code generator; the bus signal of the first state of the local control counter, the output of the code generator of the label, the single output of the trigger of the shift control is connected through the circuit "And writing labels to the input of the first bit of the register

multiplier - divisible arithmetic unit; the output of the mark selection circuit through a matching circuit is connected to the input to the zero setting of the shift control trigger and

connected to the input of the counter via the AND circuit, to which the output of the switch of the position of the comma is also connected, and with the position of the switch corresponding to fixing the comma after O, 1, 2, ..., l-1 digits of numbers, the output of the switch is connected 1, 2, ..., L + 1-bit bits of clock pulses, respectively, when dividing, and when multiplied, the output of the switch is connected, respectively, to the n-fl circuit,

n -, ..., bits

This makes it possible to reduce the equipment of the unit for controlling the multiplication and division of electronic key machines on dynamic registers.

FIG. 1 shows a device for controlling multiply and division; in fig. 2 is a typical circuit diagram of a serial arithmetic unit on dynamic registers.

The circuit contains an arithmetic unit / on dynamic registers, that is, block 2 with outputs 3 TPi, TPO, ..., TPP, and clock pulses, respectively, 1, 2, ..., "., L + 1 bits, switch

position 4, shift control trigger 5, local control counter 6, trigger setting input 7 with Shift to "O, circuit" AND label 8 entries, label allocation circuit 9, output 10 of the first state of the local control counter, output P of the fourth state No local control counter, single output 12 of the shift control trigger, AND circuit 13-15, label code generator 16, input 17 of the first bit of the multiplier register — divisible arithmetic unit, output 18 of the arithmetic unit registers, AND circuit 19.

The sequential arithmetic unit on the dynamic registers (Fig. 2) contains the permanent operand register (multiplier or divisor) 21, the adder 22, the result register 23, the multiplier register - the dividend 24.

The operation of the proposed device with cleverness, Kenya and fission differs from the operation of the known devices only in terms of determining the location of the comma as a result of these operations. For this purpose, a packet of service characters (labels) is written in the vacant spaces of the result registers and the multiplier-divisible. The length of the label packet is a function of the number of bits after the second. The number of labels to be written depends on the type of operation and the position of the decimal comma.

The mark tagging scheme is used to determine when the tagging process is finished and when the operation is completed. Multiplication and division are performed in steps. Before multiplication, counter 6 is in the first state, and the multiplicand and multiplier are placed, respectively, in registers 21 and 24. This position corresponds to the first step. Ffa second step includes a trigger 5, which controls the shift in registers 24 and 23 until in n + 1-; m register de register 24 is not a variable multiplier different from "O. For each shift, a matching M is entered in the first bit of register 24 in the first bit of register 24. This continues until the counter 6 goes to the second state after the B of the control and the selection of the mark 5. In the second state, the labels are written, since 8 ne is triggered. When labels are entered in the l + 1 st bit of register 24, a coincidence circuit 13 is triggered,

transferring 6 to the third state. In the fourth state, the counter goes by CONDITION, the last character in register 24. In the fourth state, when the label hits

in I + 1-th bit of register 23, the circuit l gives a pulse to the input of the installation of the trigger 5, the zero state. At this multiplication ends. . When dividing in the first step, the counter 6 is in the first state, and the dividend and the divisor are in registers 24 and 23. In the second step, the tr-igger 5 is set to "1 and allows shifts in registers 24 and 23. For each shift through scheme 8 in the first bit of register 24, the mark M is entered until counter 6 switches to the second state when circuit 15 is activated. When the mark hits p- | -1st bit of register 24, a coincidence circuit 13 transfers the counter to third state. In the following, a packet of n marks is interpreted by the zero word. The last character goes to register 23, and when it hits tt-f-1-th bit in the fourth state of counter 6, circuit 14 produces a pulse of setting trigger 5 to the zero state. This ends the division.

Subject invention

The control unit for multiplying and dividing binary-decimal numbers, represented in the form of a variable-fixed comma, in an arithmetic unit, containing a clocking unit associated with a local control counter, a switch

the position of the comma, the information shift control trigger and the logic circuits, characterized in that, for the purpose of simplification, it contains an " tag and record recording scheme, a tag extraction scheme and a tag code generator; a tire

the signal of the first state of the local control counter, the output of the tag code generator, the single output of the shift control flip-flop, are connected via the AND label label circuit to the input of the first register bit

multiplier - divisible arithmetic unit; the output of the & And mark selection circuit is connected with the input of the installation to the shift control trigger and with the counting input through the ' circuit to which the output of the commanding switch connected to the output buses of the clock unit is connected.

FIG. 2