SU363202A1 - WA:; UNION - Google Patents

Description

The invention relates to computing and can be used to convert voltage into a digital code. Known analog-to-digital converters of bit balancing, containing the clock distributor, associated with the trigger register, the output of which through the digital-analog converter is connected with the input of the comparison device, do not provide control. In the proposed analog-to-digital converter, the control is achieved by the fact that it contains an indication trigger with an innicator device, a memory trigger, a matching circuit, an assembly circuit and a reset device, with the output of the distributor connected to the higher-order trigger register being connected to a single memory trigger input, the output of the comparison device is connected to the zero memory trigger input through an assembly circuit, and the output of the distributor connected to the low-level trigger and the memory trigger output via the sat circuit Orcs are connected to a single input trigger trigger. the zero input of the memory trigger through the assembly scheme, and the trigger of the indication is not positive, they are simply connected to the output of the device - Reset. The drawing shows the block diagram of the proposed analog-to-digital Converter. The analog-to-digital converter contains a device / comparison; trigger register 2; digital-to-analog converter 5; distributor 4 sync potentials; trigger 5 memory; match circuit 6; assembly circuit 7; trigger 8 indication; indicator device 9; device 10 reset. The first clock potential from the distributor 4 transfers the trigger of the higher bit of register 2 from the state "O to the state" 1 and at the same time - the trigger 5 memory from the state "O to the state" 1. The output of the memory trigger 5 is connected to the input of the matching circuit 6. The L-sync potential translates the low-order trigger of register 2 from state "O to state" 1 and simultaneously arrives at the other input of circuit 6 of coincidence. When the pulses coincide with the output of the distributor and the output of the memory trigger 5, a short pulse appears at the output of the coincidence circuit 6, which flips the trigger 8 indicacin from the state "O to the state" 1 and fixes the delayed time coincidence of the pulses at the input of circuit 6 coincidence n; virtually any amount of time. This 1 state of the trigger 8 of the indication is signaled by the indicator device 9. If during the time of conversion the measured value is

voltage And there was less voltage: 1о: М1пен1сИЦии Uk, then at the output of the control / comparison, a recompletion signal appears, which relocates the corresponding trigger register 2 to the initial state and simultaneously, through the circuit 7 of the assembly, reloads trigger 5 (Memory to the original In this case, when the synchronous potential appears at the input of circuit 6, there will be no coincidence at its output.

If, during the conversion time, the measured voltage was greater than the compensation voltage U, the device / comparison does not produce an overcompensation signal. No trigger register 2 is reset to its original state, so register 2 is completely full and it is impossible to determine if the resulting digital code corresponds to the measured voltage. Thus, the overcompensation signal is a criterion for estimating register overflow 2.

- The condition “dumping” can be reset using the reset device 10. The reset voltage is applied to the "O input of the trigger 8 of the display and through the circuit 7 of the assembly to the" O input of the trigger 5 of the memory.

4 Subject of the invention

A counterbalanced analog-to-digital converter containing a switchboard of their potential potentials associated with a trigger register, the output of which through a digital-to-analog converter is connected to the input of a comparator device, characterized in that, for the purpose of control, it contains a trigger indicator with an indicator device, a trigger a memory, a matching circuit, an assembly circuit and a reset device, wherein the output of the distributor connected to the high register trigger is connected to the single input of the memory trigger, the output troystva through comparing circuit assembly connected to the zero input of the memory flip-flop, and the output of the distributor, connected to the least significant bit flip-flop, and the flip-flop output memory through the coincidence circuit are connected to a single trigger input indication; the zero input, the memory trigger via the assembly circuit, and the display trigger are directly connected to the output of the reset device.