SU361528A1 - ALLBODY [02; 1АЯ * z> &PATENT;; o • <2> & j ~ w ,,., ^ Rr-., Pi L .... ^ ..: ..- • - .-. .ABIBLUY '! ci {a - Google Patents

Description

The invention relates to electronics and is intended to transmit information from several sources over a single channel, amplification, or processing by temporal separation of channels with pulse amplitude modulation. There are known devices with time division channels, which contain a channel switch, a clock pulse generator, modulators-interrupters, amplifiers, phase-sensitive level locks, and keys. The disadvantages of these devices - weak protection from high-frequency input interference and complexity. The aim of the invention is to suppress the input high-frequency noise. The goal is achieved through the use of integral modulation, in which the alternate short-circuiting of the serial switches of the switch leads to the sampling of the integral values of the signals during the non-switching period. The difference of the proposed device is also the direct connection of the outputs of the level switches to the inputs of the channel switches of the switch, the connection of the modulator outputs and the clamp with the help of a capacitor and the connection of the latter with the corresponding outputs of the distributor. FIG. 1 shows a diagram of the proposed device for temporarily compacting low level signals; on phpg. 2 - timing charts of the device. The device contains several identical channels having common output terminals /. The first channel includes input terminals 2, modulator-interrupter 3, phase inverter 4, phase-sensitive level clamp 5, integrating capacitor 6, switch 7 with control inputs 8. Modulator-interrupter 3 contains a resistor 9 and in parallel in the series circuit. circuit key 10 with control inputs //. Level 5 latch contains in series circuit a capacitor 12 and in parallel a key 13 with control m. And inputs 14. The control inputs of all keys are connected to the corresponding outputs of the clock generator 15. Similarly, terminals 16 are included in the second and third channels and 17, modulators and 18 and 19 phase inverters, amplifiers 20 and 21, phase-sensitive level locks 22 and 23, integrating capacitors 24 and 25, serial switches 26 and 27 with control inputs 28 and 29. Modules and interrupters 18 and 19 contain input resistors 30 and 31 and the parallel keys 32 and 33 with the control inputs 34 and 35. Spacers 22 and layer 23 comprise capacitors 36, 37 and side keys 38, 39 with the control inputs 40 and 41 connected to the generator 75 outputs.

Capacitor 12 (36 and 37) has a capacity ten times the capacity of capacitor 6 (24 and 25). Amplifiers 4, 20, 21 have high input and low output resistance and high gain. The day of the series-connected links 3, 4, 5 (18, 20, 22 or 19, 21,) is connected on one side to the input terminal 2 (16 or 17, respectively), and on the other side to the key 7 (26 or 27 ).

The signal clips of the keys of the torpedo module 3 (18 and 19) and the latch 5 (22 and 23) are connected by integrating capacitors 6 (24 and 25). The control inputs of the keys W and 13 (or 32 and 38; 33 and 39) are parallelized. The outputs of the switches 7, 26 and 27 are interconnected and with the output terminal 1. All KEYS are normally open and only closed when a high voltage pulse arrives at the control inputs.

The device operates as follows (see Fig. 2).

Starting from the moment of generation by the generator 15 of a pulse i / n (Ic) with a duration TI, i.e. from the moment of closing the keys 10 and 13, the output of the level clamp has a zero voltage level, and the capacitor 6 is quickly discharged to zero through small resistances of the keys . The left side of the capacitor 12 is charged to the output voltage of amplifier 4. At the time of the pulse, i.e., at time ti, the keys 10 and 13 open, and the voltage at the output of the level lock begins to increase approximately linearly.

The voltage L-ja is defined by the following expression:

t U, dt, (1)

and - -

(yj3

 I

where Ra is the resistance of the input resistor 9; Sat is the capacitance of the integrating capacitor 6;

L / 2 is the instantaneous value of the voltage at the output terminals 2 of the first channel at the current time point. The capacitance of capacitor 12 is tens or hundreds of times greater than the capacitance of capacitor 6, therefore, with a large gain factor for the voltage of the amplifier 4, the voltage f / ia is exactly equal to the right side of the expression (1), i.e., the input signal is perfectly integrated integration on a DC solver with a capacitor in a parallel feedback circuit.

At time 2, the generator 15 generates a short-term voltage pulse L / s with duration t, as a result of which the key 7 is closed and the integrator signal Uis is transmitted to the output terminal /.

At the moment of formation of the rear pulse Lg.H of opening the key 7, the generator produces a pulse (TC (f / u) with duration TI, as a result of which the keys 10 and 13 are closed again, the capacitor 6 is quickly discharged, the left side of the capacitor 12 is charged to the output the voltage of the amplifier is 4, and so on. Thus, the time interval / 2 + T2-1 is the polling period of the Tf signal of the first channel.

At the time of generating the leading edge of the pulse, the voltage f / is is determined by the expression:

t

. (.- "

(2)

where t / 2cp is the average value of the input signal over the time of the formation of the trailing edge, the voltage t / is is determined by the expression:

/ 2--2

and.

2cp

Uis

(4 + СЛ,

Cara

ti / h jwl.

(3)

  GGy

Bool

Since the pulse Us is short-term, i.e.

Tz - 1, then i3-i /; 3 ---% f / Ct / ,, p. (four)

CeAj

Therefore, at the total output of the device

temporary compaction periodically receive short duration pulses; duration T2, the amplitude of which corresponds to the average value of the input signal on the first channel for the current period.

At the same time, choosing the product less than the pre-Gu r, gain is obtained in A / C times the output AM pulses. Since the left capacitor plate / 2 after each period is charged before the output voltage of the amplifier, a slow change in the level of the amplifier (drift) does not affect the result.

The second and third channels of the device operate similarly with a time shift on Go / 3 and 2 Go / 3 with respect to the processes of the first

channel. The duration of the control keys 32, 38, 33, 39 pulses is equal to TI, the duration of the control keys 2 and 27 pulses equal to T2, and the time constants R6oCzi and / siCgs are equal to the time constant

and the polling period of the signals of both the second and third channels is equal to Guo. Therefore, at the total output of the device, a series of short pulses is obtained, spaced from each other by the time T0 / 3, whose amplitude

is equal to the amplified by K time of the average value of the input signal of the corresponding channel for the current period Gs.

The links of the circuit produce simultaneous amplification of signals, periodic calculation and correction of the drift of zero amplifiers,

i.e., the same circuit elements perform several functions at the same time.

Averaging eliminates a spurious signal in a time-compressed device generated by an input high-frequency disturbance. For example, if the interference frequency exceeds the high frequency of the useful signal five times, the magnitude of the false signal is 23.4 - 0% of the amplitude of the interference. The zero value of the low-frequency spurious signal will be obtained if any integer number of interference periods are located on the time interval 4- / i.

Effective attenuation of the high-frequency noise and amplification of the input DC signals without errors due to the zero drift of the amplifiers constitute the advantages of the described device.

The device can be used to compact the signals produced by current sources having a high output impedance (in this case, the input resistors 9, 30 and 31 of the breaker modulators can be eliminated).

The device can be built on electronic keys, on controlled electromechanical breakers, as well as using mechanical lamella switches with corresponding time diagrams (Fig. 2), the distribution of contacts.

Thus, the described device -

simple, compact and noiseproof. It

can be applied in multichannel

amplification, transmission, recording and

signal processing.

Subject invention

A device for temporarily compacting low-level signals, containing a switch of channels with serial keys, a clock generator and channels consisting of storage capacitors, modulators of breakers with parallel keys, amplifiers and phase-sensitive level switches with parallel keys, characterized in that suppressing the input high-frequency noise, the outputs of phase-sensitive level clamps are directly connected to the inputs of the serial switches of the channel switch, the signal in the current paths of parallel switches modulators-interrupters and phase-sensitive latches

the levels are interconnected through capacitors, and the control inputs of the parallel switches of the modulators-interrupters and phase-sensitive level locks are connected to the corresponding outputs of the clock generator.

W.

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